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參數(shù)資料
| 型號(hào)： | MT9046AN |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | T1/E1 System Synchronizer with Holdover |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO48 |
| 封裝： | 0.300 INCH, MO-118AA, SSOP-48 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大?。?/td> | 508K |
| 代理商： | MT9046AN |
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MT9046
Data Sheet
13
Zarlink Semiconductor Inc.
Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a
mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has
settled to a steady state.
In the case of the MT9046, the output signal phase continuity is maintained to within
±
5 ns at the instance (over
one frame) of all reference switches and all mode changes. The total phase shift, depending on the switch or type
of mode change, may accumulate up to 200 ns over many frames. The rate of change of the 200 ns phase shift is
limited to a maximum phase slope of approximately 5 ns/125 us. This meets the AT&T TR62411 maximum phase
slope requirement of 7.6 ns/125 us and Bellcore GR-1244-CORE (81 ns/1.326 ms).
Phase Lock Time
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal
and output signal are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
initial input to output phase difference
initial input to output frequency difference
synchronizer loop filter
synchronizer limiter
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT9046 loop filter and
limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently,
phase lock time, which is not a standards requirement, may be longer than in other applications. See AC Electrical
Characteristics - Performance for Maximum Phase Lock TIme.
MT9046 provides a fast lock pin (FLOCK), which, when set high enables the PLL to lock to an incoming reference
within approximately 500 ms.
MT9046 Measures of Performance
The following are some synchronizer performance indicators and their corresponding definitions.
Intrinsic Jitter
Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by
applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may
also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring
the output jitter of the device. Intrinsic jitter is usually measured with various bandlimiting filters depending on the
applicable standards. In the MT9046, the intrinsic Jitter is limited to less than 0.02 UI on the 2.048 MHz and
1.544 MHz clocks.
MTIE S
TIEmax t
( )
TIEmin t
( )
–
=
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| MT9046AN1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER T1/E1 48SSOP 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER T1/E1 48SSOP |
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