參數(shù)資料
型號： MT9043AN48PINSSOP
廠商： Zarlink Semiconductor Inc.
英文描述： T1/E1 System Synchronizer
中文描述： T1/E1的系統(tǒng)同步
文件頁數(shù)： 6/29頁
文件大小： 453K
代理商： MT9043AN48PINSSOP
MT9043
Data Sheet
6
Zarlink Semiconductor Inc.
rearrangements. Each time a reference switch is made, the delay between input signal and output signal will
change. The value of this delay is the accumulation of the error measured during each reference switch.
The programmable delay circuit can be zeroed by applying a logic low pulse to the TIE Circuit Reset (TCLR) pin. A
minimum reset pulse width is 300ns. This results in a phase alignment between the input reference signal and the
output signal as shown in Figure 13. The speed of the phase alignment correction is limited to 5ns per 125us, and
convergence is in the direction of least phase travel.
The state diagram of Figure 7 indicates the state changes during which the TIE corrector circuit is activated.
Digital Phase Lock Loop (DPLL)
As shown in Figure 4, the DPLL of the MT9043 consists of a Phase Detector, Limiter, Loop Filter, Digitally
Controlled Oscillator, and a Control Circuit.
Phase Detector
- the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the
feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase
difference between the two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the
proper feedback signal to be externally selected (e.g., 8kHz, 1.544MHz, 2.048MHz or 19.44MHz).
Limiter
- the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all
input transient conditions with a maximum output phase slope of 5ns per 125us. This is well within the maximum
phase slope of 7.6ns per 125us or 81ns per 1.326ms specified by AT&T TR62411 and Bellcore GR-1244-CORE,
respectively.
Loop Filter
- the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four
reference frequency selections (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). This filter ensures that the jitter transfer
requirements in ETS 300 011 and AT&T TR62411 are met.
Control Circuit
- the Control Circuit uses status and control information from the State Machine and the Input
Impairment Circuit to set the mode of the DPLL. The two possible modes are Normal and Freerun.
Figure 4 - DPLL Block Diagram
Digitally Controlled Oscillator (DCO)
- the DCO receives the limited and filtered signal from the Loop Filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the MT9043.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source.
Control
Circuit
State Select
from
Input Impairment Monitor
State Select
from
State Machine
Feedback Signal
from
Frequency Select MUX
DPLL Reference
to
Output Interface Circuit
Virtual Reference
from
TIE Corrector
Limiter
Loop Filter
Digitally
Controlled
Oscillator
Phase
Detector
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