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參數資料
| 型號： | MT9043AN48PINSSOP |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | T1/E1 System Synchronizer |
| 中文描述： | T1/E1的系統(tǒng)同步 |
| 文件頁數： | 4/29頁 |
| 文件大?。?/td> | 453K |
| 代理商： | MT9043AN48PINSSOP |
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MT9043
Data Sheet
4
Zarlink Semiconductor Inc.
Functional Description
The MT9043 is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which
is described in the following sections.
Reference Select MUX Circuit
The MT9043 accepts two simultaneous reference input signals and operates on their falling edges. Either the
primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE
Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1
and Table 4.
Frequency Select MUX Circuit
The MT9043 operates with one of four possible input reference frequencies (8kHz, 1.544MHz, 2.048MHz or
19.44MHz). The frequency select inputs (FS1 and FS2) determine which of the four frequencies may be used at
the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST)
must be performed after every frequency select input change. See Table 1.
38
RSEL
Reference Source Select (Input).
A logic low selects the PRI (primary) reference source as
the input reference signal and a logic high selects the SEC (secondary) input. The logic level
at this input is gated in by the rising edge of F8o. See Table 2. This pin is internally pulled
down to VSS.
39
IC
Internal Connection.
Tie low for normal operation.
40
FS2
Frequency Select 2 (Input).
This input, in conjunction with FS1, selects which of four
possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI and
SEC inputs. See Table 1.
41
FS1
Frequency Select 1 (Input).
See pin description for FS2.
42
IC
Internal Connection.
Tie Low for Normal Operation.
43
IC
Internal Connection.
Leave Open Circuit.
44
TDO
Test Serial Data Out (CMOS Output).
JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.
45
TDI
Test Serial Data In (Input).
JTAG serial test instructions and data are shifted in on this pin.
This pin is internally pulled up to V
DD
.
Test Reset (Input).
Asynchronously initializes the JTAG TAP controller by putting it in the
Test-Logic-Reset state. If not used, this pin should be held low.
46
TRST
47
TCK
Test Clock (Input).
Provides the clock to the JTAG test logic. This pin is internally pulled up
to V
DD
.
Test Mode Select (Input).
JTAG signal that controls the state transitions of the TAP
controller. This pin is internally pulled up to V
DD
.
48
TMS
Pin Description
Pin #
Name
Description
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MT9043ANR1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER T1/E1 48SSOP 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER T1/E1 48SSOP |
| MT9044 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/OC3 System Synchronizer |
| MT9044AL | 制造商:Microsemi Corporation 功能描述:FRAMER E1/OC3/T1 5V 44MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/OC3/T1 5V 44MQFP - Trays |
| MT9044AL1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1/OC3/T1 5V 44MQFP - Trays |
| MT9044AP | 制造商:Microsemi Corporation 功能描述: |
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