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參數(shù)資料
| 型號： | MT9040AN |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | T1/E1 Synchronizer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO48 |
| 封裝： | 0.300 INCH, MO-118AA, SSOP-48 |
| 文件頁數(shù)： | 9/27頁 |
| 文件大?。?/td> | 424K |
| 代理商： | MT9040AN |
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MT9040
Data Sheet
9
Zarlink Semiconductor Inc.
Capture Range
Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull
into synchronization. The MT9040 capture range is equal to
±
230 ppm minus the accuracy of the master clock
(OSCi). For example, a 32 ppm master clock results in a capture range of 198 ppm.
Lock Range
This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock
range is equal to the capture range for the MT9040.
Phase Lock Time
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal
and output signal are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
initial input to output phase difference
initial input to output frequency difference
synchronizer loop filter
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. See AC Electrical Characteristics - Performance for Maximum Phase Lock Time.
MT9040 provides a fast lock pin (FLOCK), which, when set high enables the PLL to lock to an incoming reference
within approximately 500 ms.
MT9040 and Network Specifications
The MT9040 fully meets all applicable PLL requirements (intrinsic jitter, jitter/wander tolerance, jitter/wander
transfer, frequency accuracy and capture range for the following specifications.
1. Bellcore GR-1244-CORE June 1995 for Stratum 4
2. AT&T TR62411(DS1) December 1990 for Stratum 4
3. ANSI T1.101 (DS1) February 1994 for Stratum 4
4. ETSI 300 011 (E1) April 1992
5. TBR 4 November 1995
6. TBR 12 December 1993
7. TBR 13 January 1996
8. ITU-T I.431 March 1993
Applications
This section contains MT9040 application specific details for clock and crystal operation, reset operation, power
supply decoupling, and control operation.
Master Clock
The MT9040 can use either a clock or crystal as the master timing source.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT9040AN1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Rail/Tube |
| MT9040ANR1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Tape and Reel |
| MT9041 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multiple Output Trunk PLL |
| MT9041AP | 制造商:Microsemi Corporation 功能描述:WAN/PLL 制造商:Zarlink Semiconductor Inc 功能描述:WAN/PLL |
| MT9041B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1 System Synchronizer |
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