參數(shù)資料
型號(hào): MT9040AN
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: T1/E1 Synchronizer
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO48
封裝: 0.300 INCH, MO-118AA, SSOP-48
文件頁數(shù): 6/27頁
文件大小: 424K
代理商: MT9040AN
MT9040
Data Sheet
6
Zarlink Semiconductor Inc.
Figure 4 - Output Interface Circuit Block Diagram
The frame pulse outputs (F0o, F8o, F16o, TSP, and RSP) are generated directly from the C16 clock.
The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulse and clock outputs
are locked to one another for all operating states, and are also locked to the input reference in Normal Mode. See
Figures 10,11 and 12.
All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high
capacitance (e.g., 30pF) loads.
Input Impairment Monitor
This circuit monitors the input signal to the DPLL for a complete loss of incoming signal, or a large frequency shift in
the incoming signal. If the input signal is outside the Impairment Monitor Capture Range the PLL automatically
changes from Normal Mode to Free Run Mode. See AC Electrical Characteristics - Performance for the Impairment
Monitor Capture Range. When the incoming signal returns to normal, the DPLL is returned to Normal Mode.
Master Clock
The MT9040 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
Tapped
Delay
Line
From
DPLL
T1 Divider
E1 Divider
16MHz
12MHz
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
Tapped
Delay
Line
Tapped
Delay
Line
Tapped
Delay
Line
DS2 Divider
12MHz
19MHz
C6o
C19o
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