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參數(shù)資料
| 型號： | MT9040AN |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | T1/E1 Synchronizer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO48 |
| 封裝： | 0.300 INCH, MO-118AA, SSOP-48 |
| 文件頁數(shù)： | 4/27頁 |
| 文件大?。?/td> | 424K |
| 代理商： | MT9040AN |
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MT9040
Data Sheet
4
Zarlink Semiconductor Inc.
Functional Description
The MT9040 is a T1/E1 Trunk Synchronizer, providing timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which
is described in the following sections.
Frequency Select MUX Circuit
The MT9040 operates on the falling edge of the reference. It operates with one of four possible input reference
frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). The frequency select inputs (FS1 and FS2) determine
which of the four frequencies may be used at the reference input. A reset (RST) must be performed after every
frequency select input change. See Table 1.
Table 1 - Input Frequency Selection
Digital Phase Lock Loop (DPLL)
As shown in Figure 3, the DPLL of the MT9040 consists of a Phase Detector, Loop Filter, Digitally Controlled
Oscillator and a Control Circuit.
Phase Detector
- the Phase Detector compares the reference signal with the feedback signal from the Frequency
Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error
signal is passed to the Loop Filter. The Frequency Select MUX allows the proper feedback signal to be externally
selected (e.g., 8kHz, 1.544MHz, 2.048MHz or 19.44MHz).
45
TDI
Test Serial Data In (Input).
JTAG serial test instructions and data are shifted in on this pin.
This pin is internally pulled up to V
DD
.
Test Reset (Input).
Asynchronously initializes the JTAG TAP controller by putting it in the
Test-Logic-Reset state. If not used, this pin should be held low.
46
TRST
47
TCK
Test Clock (Input).
Provides the clock to the JTAG test logic.
48
TMS
Test Mode Select (Input).
JTAG signal that controls the state transitions of the TAP controller.
FS2
FS1
Input Frequency
0
0
19.44MHz
0
1
8kHz
1
0
1.544MHz
1
1
2.048MHz
Pin Description (continued)
Pin #
Name
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9043 | T1/E1 System Synchronizer |
| MT9043AN | T1/E1 System Synchronizer |
| MT9043AN48PINSSOP | T1/E1 System Synchronizer |
| MT9045 | T1/E1/OC3 System Synchronizer |
| MT9045AN | T1/E1/OC3 System Synchronizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9040AN1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Rail/Tube |
| MT9040ANR1 | 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Tape and Reel |
| MT9041 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multiple Output Trunk PLL |
| MT9041AP | 制造商:Microsemi Corporation 功能描述:WAN/PLL 制造商:Zarlink Semiconductor Inc 功能描述:WAN/PLL |
| MT9041B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1 System Synchronizer |
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