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參數(shù)資料
| 型號： | MT8986APR |
| 廠商： | Toshiba Corporation |
| 英文描述： | CMOS ST-BUS Family Multiple Rate Digital Switch |
| 中文描述： | 意法半導(dǎo)體的CMOS總線家庭多速率數(shù)字開關(guān) |
| 文件頁數(shù)： | 6/46頁 |
| 文件大小： | 765K |
| 代理商： | MT8986APR |
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MT8986
Data Sheet
6
Zarlink Semiconductor Inc.
of the frame synchronization input signal and configures its serial port to be compatible to both ST-BUS and GCI
formats.
In the 44 pin packages, two different microprocessor bus interfaces can be selected through an input mode pin
(IM): Non-Multiplexed or Multiplexed. These interfaces provide compatibility with Intel/National multiplexed and
Motorola Multiplexed/Non-Multiplexed buses. In 44 pin, the MT8986 provides a 16 x 8 switching configuration to
form a 512 x 256 channel blocking matrix. Also, a flexible Stream Pair Selection operation allows the software
selection of which pair of input and output streams can be connected to an internal 128 x 128 matrix. See Switching
Configurations section for details.
Functional Description
A functional Block Diagram of the MT8986 device is shown in Figure 1. Depending on the application, the MT8986
device receives TDM serial data at different rates and from different number of serial streams.
Data and Connect Memories
For all data rates, the received serial data is converted to parallel format by the serial to parallel converters and
stored sequentially in a Data Memory. Depending on the selected operation programmed in the IMS (Interface
Mode Select) register, the Data Memory may have up to 512 bytes in use. The sequential addressing of the Data
Memory is performed by an internal counter which is reset by the input 8 kHz frame pulse (FR) marking the frame
boundaries of the incoming serial data streams.
Data to be output on the serial streams may come from two sources: Data Memory or Connect Memory. Locations
in the Connect Memory, which is split into HIGH and LOW parts, are associated with particular ST-BUS output
streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be
switched from an ST-BUS input as in connection mode or it can be from the Connect Memory Low as in message
mode. Data destined for a particular channel on the serial output stream is read from the Data Memory or Connect
Memory Low during the previous channel time-slot. This allows enough time for memory access and parallel to
serial conversion.
Connection and Message Modes
In connection mode, the addresses of the input source data for all output channels are stored in the Connect
memories High (CMH) and Low (CML). The CML and CMH are mapped so that each location corresponds to an
output channel on the output streams. The number of source address bits in CMH and CML to be utilized varies
according to the switching configuration selected in the IMS register. For details on the use of the source address
data (CAB and SAB bits), see CMH and CML bit descrip-tion (Figures 5 & 6). Once the source address bits are
programmed by the CPU, the contents of the Data Memory at the selected address are transferred to the parallel-
to-serial converters. By having the output channel specify the source channel through the connect memory, the
user can route the same input channel to several output channels, allowing broadcast facility within the switch.
In message mode the CPU writes data to the Connect Memory Low locations corresponding to the output link and
channel number. The contents of the Connect Memory Low are transferred directly to the parallel-to-serial
converter one channel before it is to be output. The Connect Memory Low data is transmitted on to the output every
frame until it is changed by the CPU with a new data.
The features of each output channel in the MT8986 are controlled by the Connect Memory High bits. These bits
determine individual output channels to be in message or connection mode, select throughput delay types and
enable/disable output drivers. The Connect Memory High also provides additional stream and channel address bits
for some configurations. In addition, the Connect Memory High provides one bit to allow the user to control the
CSTo output in 2.048 Mb/s applications.
If an output channel is set to high-impedance, the TDM serial stream output will be placed in high impedance during
that channel time. In addition to the per-channel control, all channels on the TDM outputs can be placed in high
impedance by pulling the ODE input pin LOW. This overrides the individual per-channel programming by the
Connect Memory High bits.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT8986AP1 | CMOS ST-BUS Family Multiple Rate Digital Switch |
| MT8986AP | CMOS ST-BUS Family Multiple Rate Digital Switch |
| MT8986AL | CMOS ST-BUS Family Multiple Rate Digital Switch |
| MT8986 | CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch |
| MT8986AC | CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8986APR1 | 制造商:Microsemi Corporation 功能描述:SWITES 44PLCC - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC |
| MT8992BC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Digital Telephone with HDLC |
| MT8993BC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Digital Telephone with HDLC |
| MT89L80 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Digital Switch |
| MT89L80AN | 制造商:Microsemi Corporation 功能描述: |
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