參數(shù)資料
型號(hào)： MT8986APR
廠商： Toshiba Corporation
英文描述： CMOS ST-BUS Family Multiple Rate Digital Switch
中文描述： 意法半導(dǎo)體的CMOS總線家庭多速率數(shù)字開關(guān)
文件頁數(shù)： 11/46頁
文件大小： 765K
代理商： MT8986APR
MT8986
Data Sheet
11
Zarlink Semiconductor Inc.
Different I/O Data Rates
Except for 2 Mb/s to 4 Mb/s and 2 Mb/s to 8 Mb/s rate conversion operations, the throughput delay in the MT8986
may vary according to the output stream used for switching.
Table 3b explains the worst case conditions for the throughput delay when different I/O data rate switching
configurations are used.
Table 3b - Min/Max Throughput Delay Values for Different I/O Rate Applications
Notes:
dmin and dmax are measured in time-slots and at the point in time when the output channel is completely shifted out.
t.s. = time-slot
fr. = 125
μ
s frame
2 Mb/s t.s. = 3.9
μ
s
4 Mb/s t.s. = 1.95
μ
s
8 Mb/s t.s. = 0.975
μ
s
Constant Throughput Delay mode (V/C bit = 1)
In this mode frame sequence integrity is maintained in both Identical and Different I/O Data Rate operations by
making use of a multiple Data-Memory buffer technique. The input channels written in any of the buffers during
frame N will be read out during frame N+2. In applications at 2.048 Mb/s for instance, the minimum throughput
delay achievable in constant delay mode will be 32 time-slots; for example, when input time-slot 32 (channel 31) is
switched to output time-slot 1 (channel 0). Likewise, the maximum delay is achieved when the first time slot in a
frame (channel 0) is switched to the last time-slot in the frame (channel 31), resulting in 94 time-slots of delay.
To summarize, any input time-slot from input frame N will always be switched to the destination time-slot on output
frame N+2. Table 4 describes the MT8986 constant throughput delay values for different data rates.
Table 4 - Constant Throughput Delay values
I/O Data Rate
Configuration
Output Stream Used
0, 1
2, 3
4, 5
6, 7
2 Mb/s to 4 Mb/s
dmin=5x 4Mb/s t.s.
dmax=1 fr.+(4x 4Mb/s t.s.)
dmin=9x 8Mb/s t.s.
dmax=1 fr.+(8x 8Mb/s t.s.)
dmin=3x 2Mb/s t.s.
dmax=1 fr.+(2x 2Mb/s t.s.)
dmin=3x 2Mb/s t.s.
dmax=1 fr.+(2x 2Mb/s
2 Mb/s to 8 Mb/s
4 Mb/s to 2 Mb/s
dmin=(2x 2Mb/s t.s.)+(1x 4Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s t.s.)+(1x 4Mb/s t.s.)
dmin=(2x 2Mb/s t.s.)+
(2x 8Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s
t.s.)+(2x 8Mb/s t.s.)
8 Mb/s to 2 Mb/s
t.s.)
dmin=(2x 2Mb/s t.s.)+
(3x 8Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s
t.s.)+(3x 8Mb/s t.s.)
dmin=(2x 2Mb/s t.s.)+
(1x 8Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s
t.s.)+(1x 8Mb/s t.s.)
Data Rate
Throughput Delay (d)
2.048 Mb/s
d=[32 + (32 - IN) + (OUT - 1)]; (expressed in # time-slots)
2.048 Mb/s time-slot: 3.9
μ
s
IN: input time-slot (from 1 to 32)
OUT: output time-slot (from 1 to 32)
d=[64 + (64 - IN) + (OUT - 1)]; (expressed in # time-slots)
4.096 Mb/s time-slot: 1.95
μ
s
IN: input time-slot (from 1 to 64)
OUT: output time-slot (from 1 to 64)
d=[128 + (128 - IN) + (OUT - 1)]; (expressed in # time-slots)
8.192 Mb/s time-slot: 0.975
μ
s
IN: input time-slot (from 1 to 128)
OUT: output time-slot (from 1 to 128)
4.096 Mb/s
8.192 Mb/s
相關(guān)PDF資料
PDF描述
MT8986AP1 CMOS ST-BUS Family Multiple Rate Digital Switch
MT8986AP CMOS ST-BUS Family Multiple Rate Digital Switch
MT8986AL CMOS ST-BUS Family Multiple Rate Digital Switch
MT8986 CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch
MT8986AC CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT8986APR1 制造商:Microsemi Corporation 功能描述:SWITES 44PLCC - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC
MT8992BC 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Digital Telephone with HDLC
MT8993BC 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Digital Telephone with HDLC
MT89L80 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS ST-BUS⑩ FAMILY Digital Switch
MT89L80AN 制造商:Microsemi Corporation 功能描述:
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