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參數(shù)資料
| 型號： | MT8986AP |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch |
| 中文描述： | 意法半導體的CMOS總線⑩家庭多速率數(shù)字開關 |
| 文件頁數(shù)： | 21/46頁 |
| 文件大?。?/td> | 765K |
| 代理商： | MT8986AP |
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MT8986
Data Sheet
21
Zarlink Semiconductor Inc.
Frame Input Offset Register - Read/Write
Figure 8 - Frame Input Offset (FIO) Register
x=Don’t care
Applications
Switch Matrix Architectures
The MT8986 is an ideal device for designs of medium size switch matrix. For applications where voice and grouped
data channels are transported within the same frame, the voice samples have to be time interchanged with a
minimum delay while maintaining the integrity of grouped data. To guarantee the integrity of grouped data during
switching and to provide a minimum delay for voice connections, the MT8986 provides the per-channel selection
between variable and constant throughput delay. This can be selected by the V/C bit of the Connection Memory
High locations.
Different connectivities at different data rates can be built to accommodate Non-Blocking matrices of up to 512
channels while maintaining the per channel selection of the device's throughput delay. Some examples of such
Non-Blocking configurations are given in Figures 9 to 11.
For applications where voice and data samples are encoded into individual 64 kb/s time-slots on an 8 kHz frame
basis, the switch matrix can operate with time interchange procedures where only variable throughput delay is
guaranteed. For such applications, the MT8986 device allows cost effective implementations of Non-Blocking
matrices ranging up to 1024 channels. Figures 12 and 13 show the block diagram of implementations with Non-
Blocking capacities of 512 and 1024-channel, respectively.
BIT
7-5
NAME
OFB2-0
DESCRIPTION
Offset Bits 2-0
. These three bits define the time it takes the Serial Interface receiver to recognize
and store the first bit of the serial input streams; i.e., to start assuming a new internal frame. The
input frame offset can be selected to be up to 4 CK clock periods from the time when frame pulse
input signal is applied to the FR input.
OFB2
OFB1
OFB0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Number of Clock Periods
Normal Operation. No bit offsetting.
1
2
3
4
Reserved
Reserved
Reserved
If frame input offset operation is not required, this register should be cleared by the CPU during system initialization.
OFB2
OFB1
OFB0
X
X
X
X
X
7
6
5
4
3
2
1
0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT8986AP1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 5V 44P - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC |
| MT8986APR | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:CMOS ST-BUS Family Multiple Rate Digital Switch |
| MT8986APR1 | 制造商:Microsemi Corporation 功能描述:SWITES 44PLCC - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC |
| MT8992BC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Digital Telephone with HDLC |
| MT8993BC | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Digital Telephone with HDLC |
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