參數(shù)資料
型號(hào)： MT8986AL
廠商： Mitel Networks Corporation
英文描述： CMOS ST-BUS⑩ FAMILY Multiple Rate Digital Switch
中文描述： 意法半導(dǎo)體的CMOS總線⑩家庭多速率數(shù)字開(kāi)關(guān)
文件頁(yè)數(shù)： 9/46頁(yè)
文件大小： 765K
代理商： MT8986AL
MT8986
Data Sheet
9
Zarlink Semiconductor Inc.
frame. The interface clock for this operation should be 8.192 MHz. Figure 20 shows the timing for 8.192 Mb/s
operation.
Table 1 summarizes the MT8986 switching configurations for identical I/O data rates.
Table 1 - Switching Configurations for Identical Input and Output Data Rates
* - only in the 44 pin packages
Different Input/Output Data Rates
When Different I/O rate is selected by the DMO bit, the input and output data rates should be selected at the IDR
and ODR bits, respectively. The Switching Configuration Bits (SCB) are ignored with this operation. This selection
allows the user to multiplex conventional 2.048 Mb/s serial streams into two higher rates and vice-versa. In addition
to the rate conversion itself, the MT8986 allows for a complete 256 x 256 channel non-blocking switch at different
rates. In this operation, the per-channel variable/constant throughput delay selection is provided.
Depending on which data rates are programmed for input and output streams, the number of data streams used on
the input and output as well as the serial interface clock (CLK input pin) is different. Once the CPU defines the data
rates at the IDR and ODR bits, the MT8986 automatically configures itself with the appropriate number of input and
output streams for the desired operation. Table 2 summarizes the four options available when MT8986 is used with
different I/O rates. Figures 22 to 25 show the timing for each of the four modes shown in Table 2.
Table 2 - Switching Configurations for Different I/O Data Rates
Input Frame Offset Selection
When 4.096 or 8.192 Mb/s serial interfaces are selected, the MT8986 device provides a feature called Input Frame
Offset allowing the user to compensate for the varying delays at the incoming serial inputs while building large
Serial
Interface
Data Rate
Interface
Clock
required at
CLK Pin
(MHz)
Number of
Input x
Output
Streams
Matrix
Channel
Capacity
Input/Output
Streams Used
Variable/
Constant
throughput
Delay
Selection
2 Mb/s
2 Mb/s
*
2 Mb/s
*
4.096
4.096
8x8
16x8
*
10x10
*
256x256 Non-Blocking
512x256 Blocking
STi0-7/STo0-7
STi0-15/STo0-7
Yes
No
4.096
128x128 Non-Blocking
(only 4 input x 4-output
can be selected)
512x256 Nibbles
STi0-9/STo0-9
Yes
Nibble
Switching
(2 Mb/s)
4 Mb/s
4 Mb/s
8 Mb/s
4.096
8x4
STi0-7/STo0-3
No
4.096
4.096
8.192
8x4
4x4
2x2
512x256 Blocking
256x256 Non-Blocking
256x256 Non-Blocking
STi0-7/STo0-3
STi0-3/STo0-3
STi0-1/STo0-1
No
Yes
Yes
Input and Output
Data Rates
Interface
Clock
required at
CLK Pin
(MHz)
4.096
8.192
4.096
8.192
Number
of Input
x Output
Streams
Matrix
Channel Capacity
Input/Output
Streams Used
Variable/
Constant
throughput
Delay Selection
2 Mb/s to 4 Mb/s
2 Mb/s to 8 Mb/s
4 Mb/s to 2 Mb/s
8 Mb/s to 2 Mb/s
8x4
8x2
4x8
2x8
256x256 Non-Blocking
256x256 Non-Blocking
256x256 Non-Blocking
256x256 Non-Blocking
STi0-7/STo0-3
STi0-7/STo0-1
STi0-3/STo0-7
STi0-1/STo0-7
Yes
Yes
Yes
Yes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT8986AL1 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 5V 44M - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 5V 44M - Trays
MT8986AP 制造商:Microsemi Corporation 功能描述:
MT8986AP1 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 256 X 256/512 X 256/128 X 128 131.072MBPS 5V 44P - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC
MT8986APR 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:CMOS ST-BUS Family Multiple Rate Digital Switch
MT8986APR1 制造商:Microsemi Corporation 功能描述:SWITES 44PLCC - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC 制造商:Microsemi Corporation 功能描述:IC TDM/TSI SWITCH 512X256 44PLCC
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