參數(shù)資料
型號： MT8966
廠商： Zarlink Semiconductor Inc.
元件分類： Codec
英文描述： Integrated PCM Filter Codec
中文描述： 集成的PCM編解碼器
文件頁數(shù)： 6/32頁
文件大?。?/td> 607K
代理商： MT8966
MT8960/61/62/63/64/65/66/67
Data Sheet
6
Zarlink Semiconductor Inc.
2
C
16.5 + S
V
Ref
X
[(
128
32
)]
±
V
OFFSET
C
≠
0
where
C
= chord number (0-7)
S
= step number (0-15)
V
Ref
is a high impedance input with a varying capacitive load of up to 40 pF.
The recommended reference voltage for the MT8960 series of codecs is 2.5 V
±
0.5%. The output voltage from the
reference source should have a maximum temperature coefficient of 100 ppm/C
°
. This voltage should have a total
regulation tolerance of
±
0.5% both for changes in the input voltage and output loading of the voltage reference
source. A voltage reference circuit capable of meeting these specifications is shown in Figure 5. Analog
Devices’AD1403A voltage reference circuit is capable of driving a large number of codecs due to the high input
impedance of the V
Ref
input. Normal precautions should be taken in PCB layout design to minimize noise coupling
to this pin. A 0.1
μ
F capacitor connected from V
Ref
to ground and located as close as possible to the codec is
recommended to minimize noise entering through V
Ref
. This capacitor should have good high frequency
characteristics.
Figure 5 - Typical Voltage Reference Circuit
Timing
The codec operates in a synchronous manner (see Figure 9a). The codec is activated on the first positive
edge of
C2i after F1i has gone low. The digital output at DSTo (which is a three-state output driver) will then change from
a high impedance state to the sign bit of the encoded PCM word to be output. This will remain valid until the next
positive edge, when the next most significant bit will be output.
On the first negative clock edge (after F1i signal has been internally synchronized and CA is at GNDD or V
EE
) the
logic signal present at DSTi will be clocked into the input shift register as the sign bit of the incoming PCM word.
The eight-bit word is thus input at DSTi on negative edges of C2i and output at DSTo on positive edges of C2i.
F1i must return to a high level after the eighth clock pulse causing DSTo to enter high impedance and
preventing further input data to DSTi. F1i will continue to be sampled on every positive edge of C2i. (Note: F1i may
subsequently be taken low during the same sampling frame to enable entry of serial data into CSTi. This occurs
usually mid-frame, in conjunction with CA=V
DD
, in order to enter an 8-bit control word into Register B. In this case,
PCM input and output are inhibited by CA at V
DD
.)
Internally the codec will then perform a decode cycle on the newly input PCM word. The sampled and held analog
signal thus decoded will be updated 25
μ
s from the start of the cycle. After this the analog input from the filter is
sampled for 18
μ
s, after which digital conversion takes place during the remaining 82
μ
s of the sampling cycle.
NC
1
2
3
4
5
6
7
8
AD1403A
+5 V
2.5 V
0.1
μ
F
V
Ref
MT8960-67
FILTER/CODEC
NC
NC
NC
NC
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
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MT8966ASR1 制造商:Microsemi Corporation 功能描述:AUD CODEC 1ADC / 1DAC 20SOIC W - Tape and Reel 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CODEC U-LAW CCITT PCM 20SOIC 制造商:Microsemi Corporation 功能描述:IC CODEC U-LAW CCITT PCM 20SOIC
MT8967 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Integrated PCM Filter Codec
MT8967AS 制造商:Microsemi Corporation 功能描述:
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