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參數(shù)資料
| 型號： | MT88L70AE1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 信令電路 |
| 英文描述： | 3 Volt Integrated DTMF Receiver |
| 中文描述： | TELECOM, DTMF SIGNALING CIRCUIT, PDIP18 |
| 封裝： | PLASTIC, MS-001AC, DIP-18 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 474K |
| 代理商： | MT88L70AE1 |
MT88L70
Data Sheet
2
Zarlink Semiconductor Inc.
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
18
20
1
1
IN+
Non-Inverting Op-Amp (Input).
2
2
IN-
Inverting Op-Amp
(Input)
.
3
3
GS
Gain Select.
Gives access to output of front end differential amplifier for connection of
feedback resistor.
4
4
V
Ref
Reference Voltage (Output).
Nominally V
DD
/2 is used to bias inputs at mid-rail (see Figure 5
and Figure 6).
5
5
INH
Inhibit (Input).
Logic high inhibits the detection of tones representing characters A, B, C and
D. This pin input is internally pulled down.
6
6
PWDN
Power Down (Input).
Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
7
8
OSC1
Clock
(Input)
.
8
9
OSC2
Clock
(Output)
. A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
9
10
V
SS
Ground
(Input)
. 0 V typical.
10
11
TOE
Three State Output Enable (Input).
Logic high enables the outputs Q1-Q4. This pin is pulled
up internally.
11-
14
12-
15
Q1-Q4
Three State Data (Output).
When enabled by TOE, provide the code corresponding to the
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
15
17
StD
Delayed Steering (Output).
Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below V
TSt
.
Early Steering (Output).
Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to
a logic low.
16
18
ESt
1
2
3
4
5
6
7
8
9
10
18
17
16
15
14
13
12
11
IN+
IN-
GS
VRef
INH
PWDN
OSC1
OSC2
VSS
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
18 PIN PDIP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
INH
PWDN
NC
OSC1
OSC2
VSS
20 PIN SSOP
VDD
St/GT
ESt
StD
NC
Q4
Q3
Q2
Q1
TOE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT88L70AE | 3 Volt Integrated DTMF Receiver |
| MT88L70AN | 3 Volt Integrated DTMF Receiver |
| MT88L70AN1 | 3 Volt Integrated DTMF Receiver |
| MT88L70ASR | 3 Volt Integrated DTMF Receiver |
| MT88L70ASR1 | 3 Volt Integrated DTMF Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT88L70AN | 制造商:Microsemi Corporation 功能描述: |
| MT88L70AN1 | 制造商:Microsemi Corporation 功能描述:DTMF RX 3.58MHZ CMOS 3V 20SSOP - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC 3V INTEGRATED DTMF RCVR |
| MT88L70ANR | 制造商:Microsemi Corporation 功能描述: |
| MT88L70ANR1 | 制造商:Microsemi Corporation 功能描述:DTMF RX 3.58MHZ CMOS 3V 20SSOP - Tape and Reel 制造商:Microsemi Corporation 功能描述:PB FREE 3 VOLT INTEGRATED DTMF RECEIVER |
| MT88L70AS | 制造商:Microsemi Corporation 功能描述: |
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