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Advance Information
MT88E46
3
10
DATA
3-Wire FSK Interface Data (CMOS Logic Output).
Space frequency corresponds to logical 0.
Mark frequency corresponds to logical 1.
In interface mode 0 (when the CB0 pin is logic low) the FSK serial bit stream is output to DATA
directly.
In interface mode 1 (when the CB0 pin is logic high) the start bit is stripped off, the data byte
and the trailing stop bit are stored in a 9 bit buffer. At the end of each word indicated by the DR
signal at the DR/DET pin, the microcontroller should shift the byte out to DATA by applying 8
read pulses to the DCLK pin. A 9th DCLK pulse will shift out the trailing stop bit for framing
error checking.
11
DR/DET
3-Wire FSK Interface Data Ready/CAS Detect (CMOS Logic Output).
This is a dual purpose pin which indicates the end of an FSK word or the end of CAS.
Active low.
Data Ready:
FSK interface modes 0 and 1, it is normally high and goes low for half a bit time at the end of a
word. In mode 1 if DCLK starts while DR is low, the first rising edge of the DCLK input will
return DR to high. This feature allows an interrupt requested by a low going DR to be cleared
upon reading the first DATA bit.
When FSK demodulation is enabled this pin denotes the end of a word. In both
CAS Detect:
(nominal) to indicate that CAS has been detected.
When CAS detection is enabled, this pin goes low after the end of CAS for 416
μ
s
12
IC
Internal Connection.
Must be left open circuit.
13
NC
No Connection.
This pin is not bonded to the die and is unaffected by external connections.
14
CD
Carrier Detect (CMOS Logic Output).
A logic low indicates that an FSK signal is present. A 10ms time hysteresis has been provided
to allow for momentary signal discontinuity. The demodulated FSK data is ignored until carrier
detect has been activated.
Active low.
15
Vdd
Positive Power Supply.
and Vss pins.
A decoupling capacitor should be connected directly across the Vdd
16
CB1
Control Bit 1 (CMOS Logic Input).
CAS detection. See Tables 1 and 2.
Together with CB2 this pin enables FSK demodulation or
17
CB2
Control Bit 2 (CMOS Logic Input).
CAS detection. See Tables 1 and 2.
Together with CB1 this pin enables FSK demodulation or
18
GS2
Gain Select 2 (Output).
connect the MT88E46 to the receive pair of the telephone hybrid or speech IC. The signal can
be amplified or attenuated at GS2 via selection of the feedback resistor between GS2 and IN2-
.
This is the output of the GS2 op-amp. The op-amp should be used to
When the application is a telephone adjunct box where there is no hybrid or speech IC, if the
GS2 gain with respect to Tip/Ring is to be set to the same as that of GS1, the GS2 op-amp can
be connected as a voltage follower to the GS1 op-amp output (see Figure 5).
The GS2 signal is used for ‘off hook mode’ CAS detection only as selected via the CB1 and
CB2 pins. See Tables 1 and 2.
19
IN2-
GS2 Op-Amp Inverting Input.
of the telephone hybrid or speech IC.
The op-amp is for connecting the MT88E46 to the receive pair
20
IN2+
GS2 Op-Amp Non-Inverting Input.
pair of the telephone hybrid or speech IC.
The op-amp is for connecting the MT88E46 to the receive
Pin Description
Pin #
Name
Description