參數(shù)資料
型號(hào): MT88E46AS
廠商: ZARLINK SEMICONDUCTOR INC
元件分類(lèi): 無(wú)繩電話/電話
英文描述: Bellcore Compliant Calling Number Identification Circuit
中文描述: TELEPHONE CALLING NO IDENT CKT, PDSO20
封裝: 0.300 INCH, MS-013AC, SOIC-20
文件頁(yè)數(shù): 16/23頁(yè)
文件大?。?/td> 522K
代理商: MT88E46AS
MT88E46
Advance Information
16
AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
*Notes:
1.Tip/Ring input signal level.
dBm = decibels above or below a reference power of 1mW into 600 ohms. 0dBm = 0.7746Vrms.
dBV = decibels above or below a reference voltage of 1Vrms. 0dBV = 1Vrms.
2.GS1 op-amp configured to 0dB gain for Vdd=5V
±
10%, -4dB (preliminary) for Vdd=3V
±
10%.
3.Both mark and space have the same amplitude.
4.Band limited random noise (300-3400Hz). Present when FSK signal is present.
Electrical characteristics are over recommended operating conditions, unless otherwise stated.
AC Electrical Characteristics
- FSK Demodulation
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
Accept Signal Level
-40
-37.78
10.0
-
-6.45
-4.23
476
dBV
dBm
mVrms
1, 2
2
Bell 202 Format Reject Signal Level
-
-
-50.46
-48.24
3
dBV
dBm
mVrms
1, 2, 3
3
Transmission Rate
1188
1200
1212
baud
4
Mark and Space Frequencies
Bell 202 1 (Mark)
Bell 202 0 (Space)
CCITT V.23 1 (Mark)
CCITT V.23 0 (Space)
1188
2178
1280.5
2068.5
1200
2200
1300
2100
1212
2222
1319.5
2131.5
Hz
Hz
Hz
Hz
5
Twist: 20 log (V
MARK
/V
SPACE
)
Signal to Noise Ratio
-6
-
+10
dB
2
6
SNR
FSK
t
CP
t
CA
20
-
-
dB
2, 3, 4
7
Input FSK to CD
low delay
-
-
25
ms
See Figures 16, 17
8
Input FSK to CD
high delay
10
-
-
ms
See Figures 16, 17
9
CD Time Hysteresis
10
-
-
ms
Electrical Characteristics
- Gain Setting Amplifiers
Characteristics
Sym
Min
Max
Units
Test Conditions
1
Input Leakage Current
I
IN
R
IN
V
OS
PSRR
-
1
μ
A
M
Vss
V
IN
Vdd
2
Input Resistance
10
-
3
Input Offset Voltage
-
25
mV
4
Power Supply Rejection Ratio
30
-
dB
1kHz ripple on Vdd
5
Common Mode Rejection Ratio
CMRR
40
-
dB
V
CMmin
V
IN
V
CMmax
6
DC Open Loop Voltage Gain
A
VOL
f
C
V
O
C
L
R
L
V
CM
40
-
dB
7
Unity Gain Bandwidth
0.3
-
MHz
8
Output Voltage Swing
0.5
Vdd-0.7
V
Load
100k
9
Capacitive Load (GS1,GS2)
-
50
pF
10 Resistive Load (GS1,GS2)
100
-
k
11 Common Mode Range Voltage
1.0
Vdd-1.0
V
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