參數(shù)資料
型號： MT88E43AS
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 無繩電話/電話
英文描述： Extended Voltage Calling Number Identification Circuit 2
中文描述： TELEPHONE CALLING NO IDENT CKT, PDSO24
封裝： 0.300 INCH, MS-013AD, SOIC-24
文件頁數(shù)： 2/26頁
文件大?。?/td> 317K
代理商： MT88E43AS
MT88E43
Data Sheet
5-54
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
IN+
Non-inverting Input
of the internal opamp.
2
IN-
Inverting Input
of the internal opamp.
3
GS
Gain Select (Output)
of internal opamp. The opamp’s gain should be set according to the
nominal Vdd of the application using the information in Figure 10.
4
V
Ref
CAP
Reference Voltage (Output)
. Nominally V
DD
/2
. It is used to bias the input opamp.
Capacitor
. A 0.1
μ
F decoupling capacitor should be connected across this pin and V
SS
.
Trigger Input
. Schmitt trigger buffer input. Used for line reversal and ring detection.
5
6
TRIGin
7
TRIGRC
Trigger RC (Open Drain Output/Schmitt Input)
. Used to set the (RC) time interval from
TRIGin going low to TRIGout going high. An external resistor connected to V
DD
and capacitor
connected to V
SS
determine the duration of the (RC) time interval.
TRIGout
Trigger Out
(CMOS Output).
Schmitt trigger buffer output. Used to indicate detection of line
reversal and/or ringing.
8
9
MODE
3-wire interface: Mode Select (CMOS Input)
. When low, selects interface mode 0. When high,
selects interface mode 1. See pin 16 (DCLK) description to understand how MODE affects the
DCLK pin.
10
OSCin
Oscillator Input
. A 3.579545MHz crystal should be connected between this pin and OSCout. It
may also be driven directly from an external clock source.
11
OSCout
Oscillator Output
. A 3.579545MHz crystal should be connected between this pin and OSCin.
When OSCin is driven by an external clock, this pin should be left open.
12
V
SS
IC
Power Supply Ground
.
13
Internal Connection
. Must be connected to V
SS
for normal operation.
Power Down (Schmitt Input)
. Active high. When high, the device consumes minimal power by
disabling all functionality except TRIGin, TRIGRC and TRIGout. Must be pulled low for device
operation.
14
PWDN
15
FSKen
FSK Enable (CMOS Input)
. Must be high for FSK demodulation. This pin should be set low to
prevent the FSK demodulator from reacting to extraneous signals (such as speech, alert signal
and DTMF which are all in the same frequency band as FSK).
16
DCLK
3-wire Interface: Data Clock (CMOS Input/Output)
. In mode 0 (MODE pin low), this pin is an
output. In mode 1 (MODE pin high), this pin is an input.
17
DATA
3-wire Interface: Data (CMOS Output)
. In mode 0 data appears at the pin once demodulated.
In mode 1 data is shifted out on the rising edge of the microcontroller supplied DCLK.
VDD
St/GT
ESt
StD
INT
CD
DR
DATA
DCLK
FSKen
PWDN
IC
IN+
IN-
GS
VRef
CAP
TRIGin
TRIGRC
TRIGout
MODE
OSCin
OSCout
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
相關(guān)PDF資料
PDF描述
MT88E45B 4-Wire Calling Number Identification Circuit 2
MT88E45BN 4-Wire Calling Number Identification Circuit 2
MT88E45BS 4-Wire Calling Number Identification Circuit 2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT88E43B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Extended Voltage Calling Number Identification Circuit 2
MT88E43BE 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Extended Voltage Calling Number Identification Circuit 2
MT88E43BS 制造商:Microsemi Corporation 功能描述:
MT88E43BS1 制造商:Microsemi Corporation 功能描述:CALLER ID CMOS 3.58MHZ 3.3V/5V 24SOIC - Rail/Tube 制造商:Microsemi Corporation 功能描述:CALLING NUMBER ID CIRCUIT 2
MT88E43BSR 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Extended Voltage Calling Number Identification Circuit 2
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