參數(shù)資料
型號: MT88E43
廠商: Zarlink Semiconductor Inc.
英文描述: Extended Voltage Calling Number Identification Circuit 2
中文描述: 擴展電壓主叫號碼識別電路2
文件頁數(shù): 7/26頁
文件大?。?/td> 317K
代理商: MT88E43
Data Sheet
MT88E43
5-59
Figure 6 - Single-Ended Input
Configuration
Figure 7 - Differential Input Configuration
FSK Demodulation
The MT88E43 first bandpass filters and then
demodulates the incoming FSK signal. The carrier
detector provides an indication of the presence of
signal at the bandpass filter output. The MT88E43’s
dual mode 3-wire interface allows convenient
extraction of the 8-bit data words in the demodulated
FSK bit stream.
Note that signals such as dual tone alert signal,
speech and DTMF tones lie in the same frequency
band as FSK. They will, therefore, be demodulated
and as a result, false data will be generated. To
avoid demodulation of false data, an FSKen pin is
provided so that the FSK demodulator may be
disabled when FSK signal is not expected. There are
two events that if either is true, should be used to
disable FSKen. The events are CD returning high or
receiving all the data indicated by the message
length word.
The FSK characteristics described in Table 2 are listed
in BT and Bellcore specifications. The BT signal
frequencies correspond to CCITT V.23. The Bellcore
frequencies correspond to Bell 202. The U.K.’s CCA
requires that the TE be able to receive both CCITT
V.23 and Bell 202, as specified in the BT and Bellcore
specifications. The MT88E43 is compatible with both
formats without any adjustment.
The MT88E43 provides a powerful dual mode 3-wire
interface so that the 8-bit data words in the
demodulated FSK bit stream can be extracted
without the need either for an external UART or for
the TE/CPE’s microcontroller to perform the UART
function in software. The interface is specifically
designed for the 1200 baud rate and is comprised of
the DATA, DCLK (data clock) and DR (data ready)
pins. Two modes (modes 0 and 1) are selectable via
control of the device’s MODE pin: in mode 0, data
3-wire User Interface
C
R
IN
IN+
IN-
GS
V
Ref
Voltage Gain
(A
V
) = R
F
/ R
IN
R
F
C1
R1
C2
R4
R3
R2
R5
IN+
IN-
GS
V
Ref
Differential Input Amplifier
C1 = C2
R1 = R4 (For unity gain R5= R4)
R3 = (R2R5) / (R2 + R5)
Voltage Gain
(A
V
diff) = R5/R1 (see Figure 9,10,11)
Input Impedance
(Z
IN
diff) = 2
R1
2
+ (1/
ω
C)
2
Item
BT
Bellcore
Mark
frequency
(logic 1)
1300Hz
±
1.5%
1200Hz
±
1%
Space
frequency
(logic 0)
2100Hz
±
1.5%
2200Hz
±
1%
Received
signal level -
mark
-8dBV to
-40dBV
(-5.78dBm to
-37.78dBm)
-12dBm
a
to
-32dBm
a. The signal power is expressed in dBm referenced to 600
ohm at the CPE tip/ring (A/B) interface.
b. SR-3004,Issue 2, January 1995.
c. The frequency range is specified in GR-30-CORE.
d. Up to 20 marks may be inserted in specific places in a single
or multiple data message.
Received
signal level -
space
-8dBV to
-40dBV
-12dBm to
-36dBm
Signal level
differential
(twist)
up to 6dB
up to 10dB
b
Unwanted
signals
<= -20dB
(300-3400Hz)
<= -25dB
(0-4kHz)
c
Transmission
rate
1200 baud
±
± 1%
1200 baud
±
± 1%
Word format
1 start bit (logic
0), 8 bit word
(LSB first), 1 to
10 stop bits
(logic 1)
Table 2 - FSK Characteristics
1 start bit (logic
0), 8 bit word
(LSB first),
1 stop bit
(logic 1)
d
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相關代理商/技術參數(shù)
參數(shù)描述
MT88E43AE 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Extended Voltage Calling Number Identification Circuit 2
MT88E43AS 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Extended Voltage Calling Number Identification Circuit 2
MT88E43B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Extended Voltage Calling Number Identification Circuit 2
MT88E43BE 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Extended Voltage Calling Number Identification Circuit 2
MT88E43BS 制造商:Microsemi Corporation 功能描述: