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參數(shù)資料
| 型號： | MT8888CS |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 信令電路 |
| 英文描述： | Integrated DTMF Transceiver with Intel Micro Interface |
| 中文描述： | TELECOM, DTMF SIGNALING CIRCUIT, PDSO20 |
| 封裝： | 0.300 INCH, MS-013AC, SOIC-20 |
| 文件頁數(shù)： | 14/25頁 |
| 文件大?。?/td> | 536K |
| 代理商： | MT8888CS |
MT8888C
Data Sheet
14
Zarlink Semiconductor Inc.
BIT
NAME
DESCRIPTION
b0
BURST
Burst Mode Select. A logic high deactivates burst mode; a logic low enables burst mode.
When activated, the digital code representing a DTMF signal (see Table 1) can be written
to the transmit register, which will result in a transmit DTMF tone burst and pause of equal
durations (typically 51 msec). Following the pause, the status register will be updated (b1 -
Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been
enabled.
When CP mode (control register A, b1) is enabled the normal tone burst and pause
durations are extended from a typical duration of 51 msec to 102 msec.
When BURST is high (deactivated) the transmit tone burst duration is determined by the
TOUT bit (control register A, b0).
b1
TEST
Test Mode Control. A logic high enables the test mode; a logic low deactivates the test
mode. When TEST is enabled and DTMF mode is selected (control register A, b1=0), the
signal present on the IRQ/CP pin will be analogous to the state of the DELAYED
STEERING bit of the status register (see Figure 7, signal b3).
b2
S/D
Single or Dual Tone Generation. A logic high selects the single tone output; a logic low
selects the dual tone (DTMF) output. The single tone generation function requires further
selection of either the row or column tones (low or high group) through the C/R bit (control
register B, b3).
b3
C/R
Column or Row Tone Select. A logic high selects a column tone output; a logic low selects
a row tone output. This function is used in conjunction with the S/D bit (control register B,
b2).
Table 7 - Control Register B Description
BIT
NAME
STATUS FLAG SET
STATUS FLAG CLEARED
b0
IRQ
Interrupt has occurred. Bit one
(b1) or bit two (b2) is set.
Interrupt is inactive. Cleared after
Status Register is read.
b1
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated
and transmitter is ready for new
data.
Cleared after Status Register is
read or when in non-burst mode.
b2
RECEIVE DATA REGISTER
FULL
Valid data is in the Receive Data
Register.
Cleared after Status Register is
read.
b3
DELAYED STEERING
Set upon the valid detection of
the absence of a DTMF signal.
Cleared upon the detection of a
valid DTMF signal.
Table 8 - Status Register Description
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| MT8888CP1 | CB 5C 5#12 PIN RECP WALL |
| MT8888CN1 | ER 5C 5#16S PIN RECP WALL |
| MT8888CPR | Integrated DTMF Transceiver with Intel Micro Interface |
| MT8888CSR | Integrated DTMF Transceiver with Intel Micro Interface |
| MT8888CSR1 | Integrated DTMF Transceiver with Intel Micro Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT8888CS1 | 制造商:Microsemi Corporation 功能描述:DTMF TXRX 3.58MHz CMOS 5V 20-Pin SOIC Tube 制造商:Microsemi Corporation 功能描述:DTMF TXRX 3.58MHZ CMOS 5V 20SOIC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TXRX DTMF 20SOIC 制造商:Microsemi Corporation 功能描述:IC TXRX DTMF 20SOIC |
| MT8888CS-1 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Integrated DTMFTransceiver with Intel Micro Interface |
| MT8888CSR | 制造商:Microsemi Corporation 功能描述: |
| MT8888CSR1 | 制造商:Microsemi Corporation 功能描述:DTMF TXRX 3.58MHZ CMOS 5V 20SOIC - Tape and Reel |
| MT8889C | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Integrated DTMF Transceiver with Adaptive Micro Interface |
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