參數(shù)資料
型號: MT8888CE
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 信令電路
英文描述: Integrated DTMF Transceiver with Intel Micro Interface
中文描述: TELECOM, DTMF SIGNALING CIRCUIT, PDIP20
封裝: PLASTIC, MS-001AD, DIP-20
文件頁數(shù): 2/25頁
文件大?。?/td> 536K
代理商: MT8888CE
MT8888C
Data Sheet
2
Zarlink Semiconductor Inc.
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
20
24
28
1
1
1
IN+
Non-inverting
op-amp input.
2
2
2
IN-
Inverting
op-amp input.
3
3
4
GS
Gain Select
. Gives access to output of front end differential amplifier for
connection of feedback resistor.
4
4
6
V
Ref
V
SS
OSC1
Reference Voltage
output (V
DD
/2).
Ground (0V ).
5
5
7
6
6
8
DTMF clock/oscillator input. Connect a 4.7 M
resistor to VSS if crystal oscillator is
used.
7
7
9
OSC2
Oscillator
output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
8
10
12
TONE
Output from internal DTMF transmitter.
9
11
13
WR
Write
microprocessor input. TTL compatible.
10
12
14
CS
Chip Select
input. Active Low. This signal must be qualified externally by address
latch enable (ALE) signal, see Figure 14.
11
13
15
RS0
Register Select
input. Refer to Table 3 for bit interpretation. TTL compatible.
12
14
17
RD
Read
microprocessor input. TTL compatible.
13
15
18
IRQ/CP
Interrupt Request/Call Progress
(open drain) output. In interrupt mode, this
output goes low when a valid DTMF tone burst has been transmitted or received.
In call progress mode, this pin will output a rectangular signal representative of the
input signal applied at the input op-amp. The input signal must be within the
bandwidth limits of the call progress filter, see Figure 8.
14-17 18-21 19-22
D0-D3
Microprocessor Data Bus
. High impedance when CS = 1 or RD = 1.
TTL compatible.
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
RD
RS0
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
RD
RS0
24 PIN SSOP
20 PIN PLASTIC DIP/SOIC
28 PIN PLCC
4
5
6
7
8
9
10
11
25
24
23
22
21
20
19
G
NC
NC
NC
D3
D2
D1
D0
NC
VRef
VSS
OSC1
OSC2
NC
NC
R
3
2
1
2
2
2
1
1
1
1
1
1
1
N
I
I
V
S
E
T
W
C
R
N
I
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