參數(shù)資料
型號: MT8888CE1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 信令電路
英文描述: Integrated DTMF Transceiver with Intel Micro Interface
中文描述: TELECOM, DTMF SIGNALING CIRCUIT, PDIP20
封裝: LEAD FREE, PLASTIC, MS-001AD, DIP-20
文件頁數(shù): 9/25頁
文件大?。?/td> 536K
代理商: MT8888CE1
MT8888C
Data Sheet
9
Zarlink Semiconductor Inc.
Figure 9 - Description of Timing Events
7.0 DTMF Generator
The DTMF transmitter employed in the MT8888C is capable of generating all sixteen standard DTMF tone pairs
with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The
sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable
dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a
DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the
encoding format shown in Table 1 must be written to the transmit Data Register. Note that this is the same as the
receiver output code. The individual tones which are generated (f
LOW
and f
HIGH
) are referred to as Low Group and
High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 94 Hz. The high group
frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB
to compensate for high group attenuation on long loops.
The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length
of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched
and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time
segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate
count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time
segments is fixed at 32, however, by varying the segment length as described above the frequency can also be
varied. The divider output clocks another counter, which addresses the sinewave lookup ROM.
EXPLANATION OF EVENTS
A)
B)
C)
TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.
TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.
END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
D)
E)
F)
EXPLANATION OF SYMBOLS
V
in
ESt
St/GT
RX
0
-RX
3
b3
DTMF COMPOSITE INPUT SIGNAL.
EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
4-BIT DECODED DATA IN RECEIVE DATA REGISTER
DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A
VALID DTMF SIGNAL.
INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS
REGISTER IS READ.
INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS
CLEARED AFTER THE STATUS REGISTER IS READ.
MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.
MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.
MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.
MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.
TIME TO DETECT VALID FREQUENCIES PRESENT.
TIME TO DETECT VALID FREQUENCIES ABSENT.
GUARD TIME, TONE PRESENT.
GUARD TIME, TONE ABSENT.
b2
IRQ/CP
t
REC
t
REC
t
ID
t
DO
t
DP
t
DA
t
GTP
t
GTA
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MT8888CP 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Integrated DTMF Transceiver with Intel Micro Interface