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參數(shù)資料
| 型號(hào)： | MT8816 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | ISO-CMOS 8 x 16 Analog Switch Array |
| 中文描述： | 標(biāo)準(zhǔn)- 8 × 16的CMOS模擬開(kāi)關(guān)陣列 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 325K |
| 代理商： | MT8816 |
MT8816
Data Sheet
7
Zarlink Semiconductor Inc.
Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5 ns.
Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Refer to Appendix, Fig. A.7 for test circuit.
AC Electrical Characteristics
- Control and I/O Timings
- Voltages are with respect to V
DD
= 5 V, V
SS
= 0 V, V
EE
= -7V, unless
otherwise stated.
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Control Input crosstalk to switch
(for CS, DATA, STROBE,
Address)
CX
talk
30
mVpp
V
IN
=3 V squarewave;
R
IN
=1 k
, R
L
=10 k
.
See Appendix, Fig. A.6
2
Digital Input Capacitance
C
DI
10
pF
f=1 MHz
3
Switching Frequency
F
O
20
MHz
4
Setup Time DATA to STROBE
t
DS
10
ns
R
L
= 1 k
,
C
L
=50 pF
R
L
= 1 k
,
C
L
=50 pF
R
L
= 1 k
,
C
L
= 50pF
5
Hold Time DATA to STROBE
t
DH
10
ns
6
Setup Time Address to
STROBE
t
AS
10
ns
7
Hold Time Address to STROBE
t
AH
10
ns
R
L
= 1 k
,
C
L
=50 pF
R
L
= 1 k
,
C
L
=50 pF
R
L
= 1 k
,
C
L
=50 pF
R
L
= 1 k
,
C
L
=50 pF
R
L
= 1 k
,
C
L
=50 pF
R
L
= 1 k
,
C
L
=50 pF
R
L
= 1 k
,
C
L
=50 pF
R
L
= 1 k
,
C
L
=50 pF
8
Setup Time CS to STROBE
t
CSS
10
ns
9
Hold Time CS to STROBE
t
CSH
10
ns
10
STROBE Pulse Width
t
SPW
20
ns
11
RESET Pulse Width
t
RPW
40
ns
12
STROBE to Switch Status Delay
t
S
40
100
ns
13
DATA to Switch Status Delay
t
D
50
100
ns
14
RESET to Switch Status Delay
t
R
35
100
ns
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