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參數(shù)資料
| 型號： | MSE9S08QG8 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Mask Set Errata for Mask 3M77B |
| 中文描述： | 掩模組的勘誤表面膜3M77B |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 58K |
| 代理商： | MSE9S08QG8 |
Mask Set Errata for 9S08QG8, Mask 3M77B
8
Freescale Semiconductor
5.
Turn clocks back on by writing to CLKS[1:0]
Unexpected Operation: The prescaler divider flip-flops begin counting from the prior value rather than
startingfromzero.Thiscanresultinthecounterdetectingthefirstclockedgeafterrestarting,eitherearlier
or later than expected.
Case 8: Center-Aligned PWM, Counter is Stopped, Reset, and Restarted when Counting Up and
Count Equals the Modulo Value
Description
This case is extremely unlikely to occur in any practical application because it would be very unusual to
stop or reset the TPM counter while using center-aligned PWM mode.
1.
2.
TPM counter is counting up in center-aligned PWM mode (second half of a PWM period)
Counter is stopped (write CLKS[1:0] = 0:0) when count equals modulo value (the direction would
normally change from up counting to down counting at the next clock edge)
Counter is reset to 0x0000 by writing any value to TPMxCNTH:TPMxCNTL
Counter is turned on again by writing to CLKS[1:0]
3.
4.
Unexpected Operation: Because the internal up/down indicator was not cleared when the counter was
reset, the counter begins counting down from 0x0000 to 0xFFFF–0xFFFE… This causes the timing of the
first PWM period after the counter reset to be longer than expected.
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