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參數(shù)資料
| 型號： | MSE9S08QG8 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Mask Set Errata for Mask 3M77B |
| 中文描述： | 掩模組的勘誤表面膜3M77B |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 58K |
| 代理商： | MSE9S08QG8 |
Mask Set Errata for 9S08QG8, Mask 3M77B
Freescale Semiconductor
3
The only new instructions compared to the normal routine for flash commands are the first three
instructions, which take three bytes of code space and five bus cycles. These instructions may be located
anywhere in memory, including in the protected area of the flash memory.
ICS V1 Can Cause a Very Short Clock Pulse
SE128A-ICSV1
Description
The ICS module V1 — when configured with the FLL enabled and with BDIV set to divide-by one — can
sometimes produce a very short clock pulse. This short clock pulse can cause the device to malfunction.
The short clock pulse is caused when the digitally controlled oscillator (DCO) crosses a filter value
boundary when compensating for output frequency error. The filter value is not in the memory map and
cannot be read by user code.
When operating from the internal reference clock, certain trim values can cause the error more
often. The trim value for any particular clock frequency is unique to each device.
The temperature coefficient of the DCO is such that the unique reference frequency causing the
error, either internally or externally generated, will not be constant over temperature.
Workarounds
If using FLL enabled with internal reference (FEI) or FLL enabled with external reference (FEE)
modes, operate the device with a bus frequency equal to or below 5 MHz. This is accomplished by
setting BDIV divide-by value to two or higher (BDIV[1,0] bit field value of 01, 10 or 11).
Use the ICS in any of the modes with the FLL disabled. This includes: FLL bypassed internal (FBI),
FLL bypassed internal low power (FBILP), FLL bypassed external (FBI), FLL bypassed external
low power (FBELP) modes. (Not all devices have EXTAL and XTAL pins available to run the device
with an external reference.)
PWM Boundary Case Issues in HCS08 Timer PWM Module (TPM)
SE110-TPM
This errata describes boundary case issues that primarily affect the center-aligned PWM mode of
operation. While investigating these issues, additional, less significant, issues were discovered. These
will be explained, although they should not cause any significant problems in normal applications.
In center-aligned PWM mode, the timer counter counts up until it reaches the modulo value in
TPMMODH:TPMMODL, reverses direction, and then counts down until it reaches zero, where it reverses
and counts up again. A period of the PWM output is centered around the leading edge of the zero count
and the period is considered to start when the count changes from TPMMODH:TPMMODL–1 to
TPMMODH:TPMMODL (the same point where the counter changes from up-counting to down-counting).
The zero value and the maximum modulo value occur for only one timer count cycle each, while all other
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