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參數(shù)資料
型號: MPC9351AC
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 3/14頁
文件大?。?/td> 0K
描述: IC PLL CLOCK DRIVER LV 32-LQFP
標(biāo)準(zhǔn)包裝: 250
類型: PLL 時鐘發(fā)生器
PLL: 帶旁路
輸入: LVCMOS,LVPECL
輸出: LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 2:9
差分 - 輸入:輸出: 是/無
頻率 - 最大: 200MHz
除法器/乘法器: 是/無
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 托盤
其它名稱: 800-2256
MPC9351ACIDT-ND
MPC9351 REVISION 6 JANUARY 31, 2013
11
2013 Integrated Device Technology, Inc.
MPC9351 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
Figure 13. Propagation Delay (tPD, static phase offset)
Test Reference
Figure 14. Propagation Delay (tPD) Test Reference
Figure 15. Output Duty Cycle (DC)
Figure 16. Output-to-Output Skew tSK(O)
Figure 17. Cycle-to-Cycle Jitter
Figure 18. Period Jitter
Figure 19. I/O Jitter
Figure 20. Transition Time Test Reference
VCC
VCC 2
GND
t()
PCLK
Ext_FB
PCLK
VCMR
VCC
VCC 2
GND
VCC
VCC 2
GND
t()
TCLK
Ext_FB
The time from the PLL controlled edge to the non-controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
VCC
VCC 2
GND
tP
T0
DC = tP/T0 x 100%
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device.
VCC
VCC 2
GND
VCC
VCC 2
GND
tSK(O)
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs.
TN
TJIT(CC) = |TN–TN+1|
TN+1
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycle.s
TJIT(PER) = |TN–1/f0|
T0
TJIT() = |T0–T1mean|
TCLK
(CLK)
Ext_FB
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles.
tF
tR
VCC = 3.3 V VCC = 2.5 V
2.4
1.8 V
0.55
0.6 V
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