參數(shù)資料
型號(hào)： MPC885CZP133
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Hardware Specifications
中文描述： 硬件規(guī)格
文件頁(yè)數(shù)： 10/92頁(yè)
文件大小： 1499K
代理商： MPC885CZP133
MPC885/MPC880 Hardware Specifications, Rev. 3
10
Freescale Semiconductor
Thermal Characteristics
4
Thermal Characteristics
Table 4
shows the thermal characteristics for the MPC885/880.
5
Power Dissipation
Table 5
provides information on power dissipation. The modes are 1:1, where CPU and bus speeds are equal, and
2:1, where CPU frequency is twice bus speed.
Table 4. MPC885/880 Thermal Resistance Data
Rating
Environment
Symbol
Value
Unit
Junction-to-ambient
1
1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
2
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3
Per JEDEC JESD51-6 with the board horizontal
4
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed
pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated
value from the junction to the exposed pad without contact resistance.
6
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
Natural convection
Single-layer board (1s)
R
θ
JA 2
R
θ
JMA 3
R
θ
JMA3
R
θ
JMA3
37
°C/W
Four-layer board (2s2p)
25
Airflow (200 ft/min)
Single-layer board (1s)
30
Four-layer board (2s2p)
22
Junction-to-board
4
R
θ
JB
17
Junction-to-case
5
R
θ
JC
10
Junction-to-package top
6
Natural convection
Ψ
JT
2
Airflow (200 ft/min)
Ψ
JT
2
Table 5. Power Dissipation (P
D
)
Die Revision
Bus
Mode
CPU
Frequency
Typical
1
1
Typical power dissipation at V
DDL
= V
DDSYN
= 1.8 V, and V
DDH
is at 3.3 V.
Maximum
2
Unit
0
1:1
66 MHz
310
390
mW
80 MHz
350
430
mW
2:1
133 MHz
430
495
mW
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