參數(shù)資料
型號： MPC859TZP133
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Hardware Specifications
中文描述： 硬件規(guī)格
文件頁數(shù)： 59/92頁
文件大?。?/td> 1274K
代理商： MPC859TZP133
MOTOROLA
MPC866/859 Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
59
CPM Electrical Characteristics
12.7
SCC in NMSI Mode Electrical Specifications
Table 22 shows the NMSI external clock timings.
Table 23 shows the NMSI internal clock timings.
Table 22. NMSI External Clock Timings
Num
Characteristic
All Frequencies
Unit
Min
Max
100
RCLK1 and TCLK1 width high
1
1
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1.
2
Also applies to CD and CTS hold time when they are used as an external sync signal.
1/SYNCCLK
—
ns
101
RCLK1 and TCLK1 width low
1/SYNCCLK +5
—
ns
102
RCLK1 and TCLK1 rise/fall time
—
15.00
ns
103
TXD1 active delay (from TCLK1 falling edge)
0.00
50.00
ns
104
RTS1 active/inactive delay (from TCLK1 falling edge)
0.00
50.00
ns
105
CTS1 setup time to TCLK1 rising edge
5.00
—
ns
106
RXD1 setup time to RCLK1 rising edge
5.00
—
ns
107
RXD1 hold time from RCLK1 rising edge
2
5.00
—
ns
108
CD1 setup time to RCLK1 rising edge
5.00
—
ns
Table 23. NMSI Internal Clock Timings
Num
Characteristic
All Frequencies
Unit
Min
Max
100
RCLK1 and TCLK1 frequency
1
1
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1.
2
Also applies to CD and CTS hold time when they are used as an external sync signals.
0.00
SYNCCLK/3
MHz
102
RCLK1 and TCLK1 rise/fall time
—
—
ns
103
TXD1 active delay (from TCLK1 falling edge)
0.00
30.00
ns
104
RTS1 active/inactive delay (from TCLK1 falling edge)
0.00
30.00
ns
105
CTS1 setup time to TCLK1 rising edge
40.00
—
ns
106
RXD1 setup time to RCLK1 rising edge
40.00
—
ns
107
RXD1 hold time from RCLK1 rising edge
2
0.00
—
ns
108
CD1 setup time to RCLK1 rising edge
40.00
—
ns
F
Freescale Semiconductor, Inc.
n
.
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