參數(shù)資料
型號(hào): MPC7457
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: RISC Microprocessor Hardware Specifications
中文描述: RISC微處理器硬件規(guī)格
文件頁(yè)數(shù): 54/68頁(yè)
文件大?。?/td> 1755K
代理商: MPC7457
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
54
Freescale Semiconductor
System Design Information
requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target
system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or
push-button switches, the COP reset signals must be merged into these signals with logic.
The arrangement shown in
Figure 26
allows the COP port to independently assert HRESET or TRST, while ensuring
that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be
tied to HRESET through a 0-
isolation resistor so that it is asserted when the system reset signal (HRESET) is
asserted, ensuring that the JTAG scan chain is initialized during power-on. While Freescale recommends that the
COP header be designed into the system as shown in
Figure 26
, if this is not possible, the isolation resistor will allow
future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations.
The COP header shown in
Figure 26
adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and can be as
inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100"
centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector
key.
There is no standardized way to number the COP header shown in
Figure 26
; consequently, many different pin
numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while
others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with
an IC). Regardless of the numbering, the signal placement recommended in
Figure 26
is common to all known
emulators.
The QACK signal shown in
Figure 26
is usually connected to the PCI bridge chip in a system and is an input to the
MPC7457 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power
mode selection. In order for COP to work, the MPC7457 must see this signal asserted (pulled down). While shown
on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be
populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can
only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is deasserted
when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are
mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down operation,
QACK should be merged via logic so that it also can be driven by the PCI bridge.
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