參數(shù)資料
型號(hào): MPC18730EP
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Power Management IC with Five Regulated Outputs Programmed Through 3 Wire Serial Interface
中文描述: 與電源管理IC,通過(guò)3線串行接口編程五穩(wěn)壓輸出
文件頁(yè)數(shù): 26/35頁(yè)
文件大?。?/td> 617K
代理商: MPC18730EP
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
18730
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
VO2_SENSE[6]: Reference DAC MSB
1 = VO2_SENSE[6] on
0 = VO2_SENSE[6] off
VO2_SENSE[5]: Reference DAC Bit5
1 = VO2_SENSE[5] on
0 = VO2_SENSE[5] off
VO2_SENSE[4]: Reference DAC Bit4
1 = VO2_SENSE[4] on
0 = VO2_SENSE[4] off
VO2_SENSE[3]: Reference DAC Bit3
1 = VO2_SENSE[3] on
0 = VO2_SENSE[3] off
VO2_SENSE[2]: Reference DAC Bit2
1 = VO2_SENSE[2] on
0 = VO2_SENSE[2] off
VO2_SENSE[1]: Reference DAC Bit1
1 = VO2_SENSE[1] on
0 = VO2_SENSE[1] off
VO2_SENSE [0]: Reference DAC LSB
1 = VO2_SENSE [0] on
0 = VO2_SENSE [0] off
S_Off_VO2_SENSE: DDC2 Top side & LG (Ni_mh) /
Bottom side (Li_ion) transistor off
1 = Synchronous Rectification Off
0 = Synchronous Rectification On
Refer to
Table 11, Output Voltage of VO2_SENSE
on
page
20
for the correspondence between the output voltage
and register settings.
SREG1_V[6]: Reference DAC MSB
1 = SREG1_V[6] on
0 = SREG1_V[6] off
SREG1_V[5]: Reference DAC Bit5
1 = SREG1_V[5] on
0 = SREG1_V[5] off
SREG1_V[4]: Reference DAC Bit4
1 = SREG1_V[4] on
0 = SREG1_V[4] off
SREG1_V[3]: Reference DAC Bit3
1 = SREG1_V[3] on
0 = SREG1_V[3] off
SREG1_V[2] : Reference DAC Bit2
1 = SREG1_V[2] on
0 = SREG1_V[2] off
SREG1 [1]: Reference DAC Bit1
1 = SREG1_V[1] on
0 = SREG1_V[1] off
SREG1_V[0]: Reference DAC LSB
1 = SREG1_V[0] on
0 = SREG1_V[0] off
Reserved : Blank register bit (Freescale Pre-Defined
Register)
1 = Preferred
0 = Forbidden
Note: Do NOT change Reserved Register from default
value.
Refer to
Table 12, Output Voltage of SREG1
on page
20
for the correspondence between the output voltage and
register settings.
Table 21. VO2_SENSE Output Voltage Register
0100
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
VO2_SENSE
[6]
VO2_SENSE
[5]
VO2_SENSE
[4]
VO2_SENSE
[3]
VO2_SENSE
[2]
VO2_SENSE
[1]
VO2_SENSE
[0]
S_Off_VO2_SENSE
Default
1
0
0
0
0
0
0
0
Table 22. Regulator1 Output Voltage Register
0101
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
SREG1_V[6]
SREG1_V[5]
SREG1_V[4]
SREG1_V[3]
SREG1_V[2]
SREG1_V[1]
SREG1_V[0]
Reserved
Default
1
1
1
1
1
1
1
1
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