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參數(shù)資料
| 型號： | MK74CG117BFT |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 157K |
| 代理商： | MK74CG117BFT |
16 Output Low Skew Clock Generator
MDS 74CG117B A
4
Revision 041604
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
MK74CG117B
Power Dissipation, Termination, and Operating
Frequency
As with all clock drivers, the power dissipated by the
MK74CG117B is affected by the external loading on
the output pins. This consists of the capacitance of the
load that is being driven, as well as the PC board trace
itself. Since this capacitance must be charged and
discharged with each cycle of the output clock, as the
frequency goes up. so does the power required.
Operating below the specified maximum output clock
frequency shown in Table 2 will keep the MK74CG117B
power dissipation within acceptable limits.
External series termination resistors must be used in
series with each output. These resistors serve two
purposes: The first is to match the source impedance
to the line (PC board trace) that is being driven. This
will minimize reflections that cause non-linear
transitions on the output clock waveform. The output
impedance of the MK74CG117B is approximately 20
;
assuming a 50
line, then a 33 resistor should be
used at each output as shown in Figure 1.
Table 1. Tri-state and Mode Select
Table 2. Multiplier Selections (Input and CLK
Frequencies in MHz)
Figure 1. External Termination
As speeds rise, the limiting factor in device operation
becomes the power generated by having a large
number of drivers in one package. Using the external
termination resistors reduces the power dissipated
within the device, allowing output frequencies up to 100
MHz.
Note that the maximum operating frequency of the
MK74CG117A is determined by the Mode selected
from Table 1 and the Multiplier selected from Table 2.
For output frequencies above 83.3 MHz, all 16 outputs
must be at the same frequency (M1=M0=1).
When operating with a combination of 1X and 0.5X
outputs, the output frequency cannot exceed 83.3 MHz.
M1
M0
Mode
at
CLK(1x)
at
CLK/2(0.5x)
Max
Output
Freq.
0
All outputs,
including
REF,
tri-stated
ZZ
0
112 @ 1x,
4 @ 0.5x
CLK1–12
CLK13–16
83.3 MHz
0.8
1
08 @ 1x,
8 @ 0.5x
CLK5–12
CLK1–4,
13–16
83.3 MHz
1.25
1
16 outputs
@ 1x
CLK1–16
None
100 MHz
S2
S1 S0 Input Multiplier
CLK Out
Comments
0
33–55
0.5
16.5–25
Divider
only; no
PLL
0
1
20–50
1
20–50
PLL
0
1
0
16–40
1.25
20–50
PLL
0
1
10–50
2
20–100
PLL
1
0
8–40
2.5
20–100
PLL
1
0
1
8–30
3.333
26.7–100
PLL
1
0
8–25
4
32–100
PLL
1
8–20
5
40–10
PLL
33 ohm
To load
MK74CG117
Output
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相關(guān)代理商/技術(shù)參數(shù) |
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| MK74CG117BFTR | 功能描述:IC CLK GEN 16OUTPUT 48-SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK74ZD133 | 制造商:ICS 制造商全稱:ICS 功能描述:PLL and 32-Output Clock Driver |
| MK74ZD133F | 制造商:ICS 制造商全稱:ICS 功能描述:PLL and 32-Output Clock Driver |
| MK74ZD133FT | 制造商:ICS 制造商全稱:ICS 功能描述:PLL and 32-Output Clock Driver |
| MK74ZD133Y | 制造商:ICS 制造商全稱:ICS 功能描述:PLL and 32-Output Clock Driver |
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