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參數(shù)資料
| 型號： | MK2771-13STR |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 50 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 62K |
| 代理商： | MK2771-13STR |
MK2771-13
VCXO and Set-Top Clock Source
MDS 2771-13 A
3
Revision 110298
Printed 11/16/00
Integrated Circuit Systems 525 Race StreetSan JoseCA95126(408)295-9800telwww.icst.com
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5.0V unless noted)
Operating Voltage, VDD
4.75
5.25
V
Input High Voltage, VIH, X1 pin only
3.5
2.5
V
Input Low Voltage, VIL, X1 pin only
2.5
1.5
V
Input High Voltage, VIH (except PCS1)
2
V
Input Low Voltage, VIL (except PCS1)
0.8
V
Input High Voltage, VIH, PCS1 only
VDD-0.5
V
Input Low Voltage, VIL, PCS1 only
0.5
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load, note 2
60
mA
Short Circuit Current
Each output
±100
mA
Input Capacitance
7
pF
Frequency synthesis error
All clocks
0
ppm
VIN, VCXO control voltage
0
3
V
AC CHARACTERISTICS (VDD = 5.0V unless noted)
Input Frequency
13.500000
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At 1.4V
40
60
%
Maximum Absolute Jitter, short term
200
ps
Skew of 27 MHz outputs
Rising edges at 1.4V
-500
0
500
ps
27 MHz output pullability, note 3
0V
≤ VIN ≤ 3V
±100
ppm
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With PCLK at 50 MHz.
3. With a pullable crystal that conforms to ICS’ specifications
External Components
The MK2771-13 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1F should be connected between VDD and GND on pins 4 and 7, 6 and 7, and 15 and
14, as close to the MK2771-13 as possible. A series termination resistor of 33
may be used for each clock
output.The 13.500 MHz crystal must be connected as close to the chip as possible. The crystal should be a
parallel mode, pullable, with load capacitance of 14pF. Consult MicroClock for recommended suppliers.
See MAN05 for recommended layout of the chip and external components.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2771-15 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO and Set-Top Clock Source |
| MK2771-15R | 功能描述:IC CLK SRC VCXO/SET-TOP 28-QSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2771-15RLF | 功能描述:IC CLK SRC VCXO/SET-TOP 28-QSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MK2771-15RLFTR | 功能描述:時鐘合成器/抖動清除器 VCXO AND SET-TOP CLOCK SOURCE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2771-15RTR | 功能描述:IC CLK SRC VCXO/SET-TOP 28-QSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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