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參數(shù)資料
| 型號(hào)： | MK2049-34SITR |
| 英文描述： | 3.3 V Communications Clock PLL |
| 中文描述： | 3.3伏通信時(shí)鐘鎖相環(huán) |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 135K |
| 代理商： | MK2049-34SITR |
MK2049-34
3.3 V Communications Clock PLL
MDS 2049-34 C
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
7
Revision 121400
=connect to VDD
=connect to GND
V
G
1
2
3
4
16
15
14
13
12
11
8
9
10
18
17
20
19
cap
resist.
cap
G
V
V
resist.
resist.
cap
PC BOARD LAYOUT
A proper board layout is critical to the successful use of the MK2049. In particular, the CAP1 and CAP2 pins
are very sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as
possible and the two capacitors and resistor must be mounted next to the device as shown below. The
capacitor shown between pins 15 and 17, and the one between pins 4 and 7 are the power supply decoupling
capacitors. The high frequency output clocks on pins 8 and 9 should have a series termination of 33
connected close to the pin. Additional improvements will come from keeping all components on the same
side of the board, minimizing vias through other signal layers, and routing other signals away from the
MK2049. You may also refer to MAN05 for additional suggestions on layout of the crystal section.
The crystal traces should include pads for small capacitors from X1 and X2 to ground; these are used to
adjust the stray capacitance of the board to match the crystal load capacitance. The typical telecom reference
frequency is accurate to much less than 1 ppm, so the MK2049 may lock and run properly even if the board
capacitance is not adjusted with these fixed capacitors. However, ICS MicroClock recommends that the
adjustment capacitors be included to minimize the effects of variation in individual crystals, temperature,
and aging. The value of these capacitors (typically 0-4 pF) is determined once for a given board layout,
using the procedure described in the section titled “Determining the Crystal Frequency Adjustment
Capacitors”.
Figure 2. Typical MK2049-34 Layout
7
cap
cap
G
Optional;
see text
Cutout in ground and power plane.
Route all traces away from this area.
5
6
resist.
G
cap
cap
相關(guān)PDF資料 |
PDF描述 |
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| MK2049-35SITR | 3.3 V Communications Clock PLL |
| MK2049-36SITR | 3.3 V Communications Clock PLL |
| MK2058-01SITR | Communications Clock Jitter Attenuator |
| MK2304S-2 | ZERO DELAY, LOW SKEW BUFFER |
| MK2308-2 | ZERO DELAY LOW SKEW BUFFER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-35 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-35SI | 制造商:Integrated Device Technology Inc 功能描述:49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-35SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36SI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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