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參數(shù)資料
| 型號(hào)： | MK2049-34SITR |
| 英文描述： | 3.3 V Communications Clock PLL |
| 中文描述： | 3.3伏通信時(shí)鐘鎖相環(huán) |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 135K |
| 代理商： | MK2049-34SITR |
MK2049-34
3.3 V Communications Clock PLL
MDS 2049-34 C
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
6
Revision 121400
Measuring Zero Delay on the MK2049
The MK2049-34 produces low-jitter output clocks. In addition, this part has a very low bandwidth--on the
order of a few Hertz. Since most 8 kHz input clocks will have high jitter, this can make measuring the
input-to-output skew (zero delay feature) very difficult. The MK2049 is designed to reject the input jitter;
when the input and output clocks are both displayed on an oscilloscope, they may
appear
not to be locked
because the scope trigger point is constantly changing with the input jitter. In fact, the input and output
clocks probably are locked, and the MK2049 will have zero delay to the average position of the 8 kHz input
clock. In order to see this clearly, a low jitter 8 kHz input clock is necessary. Most lab frequency sources
are NOT SUITABLE for this since they have high jitter at low frequencies.
Frequency Locking to the Input
In all modes, the output clocks are frequency-locked to the input. The output will remain at the specified
output frequency as long as the combined variation of the input frequency and the crystal does not exceed
100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the
input frequency can vary by up to 60 ppm and still have the output clock remain frequency-locked.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-35SITR | 3.3 V Communications Clock PLL |
| MK2049-36SITR | 3.3 V Communications Clock PLL |
| MK2058-01SITR | Communications Clock Jitter Attenuator |
| MK2304S-2 | ZERO DELAY, LOW SKEW BUFFER |
| MK2308-2 | ZERO DELAY LOW SKEW BUFFER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-35 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-35SI | 制造商:Integrated Device Technology Inc 功能描述:49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-35SITR | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36SI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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