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參數(shù)資料
| 型號： | MK2049-34SAILF |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 77.76 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, SOIC-20 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 148K |
| 代理商： | MK2049-34SAILF |
3.3 Volt Communications Clock VCXO PLL
MDS 2049-34A B
5
Revision 060105
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
MK2049-34A
PC Board Layout
A proper board layout is critical to the successful use of the MK2049-34A. In particular, the CAP1 and CAP2 pins
are very sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible
and the two capacitors and resistor must be mounted next to the device as shown below. The capacitor shown
between pins 15 and 17, and the one between pins 4 and 7 are the power supply decoupling capacitors. The high
frequency output clocks on pins 8 and 9 should have a series termination of 33
connected close to the pin.
Additional improvements will come from keeping all components on the same side of the board, minimizing vias
through other signal layers, and routing other signals away from the MK2049. You may also refer to application note
MAN05 for additional suggestions on layout of the crystal selection.
The crystal traces should include pads for small capacitors from X1 and X2 to ground. These are used to adjust the
stray capacitance of the board to match the crystal load capacitance. The typical telecom reference frequency is
accurate to much less than 1 ppm, so the MK2049-34A may lock and run properly even if the board capacitance is
not adjusted with these fixed capacitors. However, ICS recommends that the adjustment capacitors be included to
minimize the effects of variation in individual crystals, temperature, and aging. The value of these capacitors
(typically 0 - 4 pF) is determined once for a given board layout, using the procedure found in application note
16
1
15
2
14
3
13
4
12
5
11
6
7
8
9
10
20
19
18
17
G
cap
resist
cap
ca
p
ca
p
resist
V
G
cap
Optional -
see text
Cutout in ground and power plane.
Route all traces away from this area.
V
= connect to VDD
G
= connect to GND
Figure 2. Typical MK2049-34 Layout
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-34SAILFTR | 功能描述:時鐘合成器/抖動清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK2049-34SAITR | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2049-34SI | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-34SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-35 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
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