參數(shù)資料
型號(hào)： MCZ33689DEWR2
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 23/31頁(yè)
文件大?。?/td> 0K
描述： IC SYSTEM BASIS CHIP LIN 32-SOIC
標(biāo)準(zhǔn)包裝： 1,000
應(yīng)用： 自動(dòng)
電流 - 電源： 5mA
電源電壓： 5.5 V ~ 18 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 32-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 32-SOIC
包裝： 帶卷 (TR)
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
33689
PIN CONNECTIONS
PIN CONNECTIONS
Figure 3. 33689 32-SOICW Pin Connections
Table 1. 33689 32-SOICW Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.
Pin
Pin Name
Formal Name
Pin Function
Definition
1, 3, 14
NC
No Connect
N/A
No internal connection to these pins.
2, 4
L1, L2
Level Inputs 1 and 2
Input
Inputs from external switches or from logic circuitry.
5–7
HS3–HS1
High-Side Driver
Outputs 3 through 1
Output
High-side (HS) drive power outputs. SPI-controlled for driving system
loads.
8, 9, 24, 25
TGND
Thermal Ground
N/A
Thermal ground pins for the device.
10
VS2
Voltage Supply 2
Input
Supply pin for the high-side switches HS1, HS2, and HS3.
11
LIN
LIN Bus
Input/Output
Bidirectional pin that represents the single-wire bus transmitter and
receiver.
12
GND
Ground
N/A
Electrical ground pin for the device.
13
VS1
Voltage Supply 1
Input
Supply pin for the 5.0 V regulator, the LIN physical interface, and the
internal logic.
15
VDD
5.0 V Regulator
Output
Output of the 5.0 V regulator.
16
AGND
Analog Ground
N/A
Analog ground pin for voltage regulator and current sense operational
amplifier.
17
VCC
Power Supply In
Input
5.0 V supply for the internal current sense operational amplifier.
18
OUT
Amplifier Output
Output
Output of the internal current sense operational amplifier.
19
E
-
Amplifier Inverted
Input
Inverted input of the internal current sense operational amplifier.
20
E+
Amplifier Non-Inverted
Input
Non-inverted input of the internal current sense operational amplifier.
21
WDC
Watchdog
Configuration
(Active Low)
Reference
Configuration pin for the watchdog timer.
TXD
1
MISO
MOSI
SCLK
TGND
IN
RST
WDC
E+
OUT
VCC
E
-
CS
RXD
INT
NC
HS3
HS2
HS1
TGND
VS2
LIN
GND
VS1
VDD
AGND
NC
L2
L1
NC
8
9
10
11
12
13
14
15
16
3
4
5
6
7
2
32
25
24
23
22
21
20
19
18
17
30
29
28
27
26
31
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