參數(shù)資料
型號: MCM69D618TQ6
廠商: MOTOROLA INC
元件分類: DRAM
英文描述: 64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM
中文描述: 64K X 18 DUAL-PORT SRAM, 6 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 7/16頁
文件大?。?/td> 175K
代理商: MCM69D618TQ6
MCM69F817
15
MOTOROLA FAST SRAM
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for PowerPC–
based and other high end MPU–based systems, these
SRAMs can be used in other high speed L2 cache or
memory applications that do not require the burst address
feature. Most L2 caches designed with a synchronous inter-
face can make use of the MCM69F817. The burst counter
feature of the BurstRAM can be disabled, and the SRAM can
be configured to act upon a continuous stream of addresses.
See Figure 5.
CONTROL PIN TIE VALUES (H
≥ VIH, L ≤ VIL)
Non–Burst
ADSP
ADSC
ADV
SE1
LBO
Sync Non–Burst,
Flow–Through SRAM
H
L
H
L
X
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
WRITES
READS
DQ
K
Q(B)
Q(A)
ADDR
AB
CD
EF
GH
W
Q(D)
Q(C)
D(E)
D(F)
D(G)
D(H)
G
Figure 5. Configured as Non–Burst Synchronous SRAM
MCM
69F817
XX
X
Motorola Memory Prefix
Part Number
Full Part Numbers — MCM69F817ZP6
MCM69F817ZP6.5
MCM69F817ZP7
MCM69F817ZP6R
MCM69F817ZP6.5R
MCM69F817ZP7R
Package (ZP = PBGA)
Blank = Trays, R = Tape and Reel
Speed (6 = 6.0 ns, 6.5 = 6.5 ns, 7 = 7.0 ns)
ORDERING INFORMATION
(Order by Full Part Number)
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參數(shù)描述
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