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參數(shù)資料
| 型號： | MCM69D618TQ6 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM |
| 中文描述： | 64K X 18 DUAL-PORT SRAM, 6 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 175K |
| 代理商： | MCM69D618TQ6 |
MCM69F817
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(3.6 V
≥ VDD ≥ 3.135 V, 70°C ≥ TA ≥ 0°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . . . .
Input Pulse Levels
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Slew Rate (See Note 1)
1.0 V/ns
. . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load
See Figure 2 Unless Otherwise Noted
. . . . . . . . . . . . . .
Output Rise/Fall Times (Max)
2.0 ns
. . . . . . . . . . . . . . . . . . . . . . . . . . .
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
P
Sb l
MCM69F817–6
150 MHz
MCM69F817–6.5
133 MHz
MCM69F817–7
117 MHz
Ui
N
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
6.7
—
7.5
—
8.5
—
ns
Clock High Pulse Width
tKHKL
2.5
—
2.5
—
3
—
ns
Clock Low Pulse Width
tKLKH
2.5
—
2.5
—
3
—
ns
Clock Access Time
tKHQV
—
6
—
6.5
—
7
ns
3
Output Enable to Output Valid
tGLQV
—
3.5
—
3.5
—
3.5
ns
3
Clock High to Output Active
tKHQX1
0
—
0
—
0
—
ns
3, 4, 5
Clock High to Output Change
tKHQX2
2
—
2
—
2
—
ns
3, 5
Output Enable to Output Active
tGLQX
0
—
0
—
0
—
ns
3, 4, 5
Output Disable to Q High–Z
tGHQZ
—
3.5
—
3.5
—
3.5
ns
3, 4, 5
Clock High to Q High–Z
tKHQZ
1
3.5
1
3.5
1
3.5
ns
3, 4, 5
Setup Times:
Address
Data In
Write
Chip Enable
ADSP, ADSC, ADV
tADKH
tDVKH
tWVKH
tEVKH
tADSKH
0.5
1.5
—
0.5
1.5
—
0.5
1.5
—
ns
Hold Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHEX
1.0
—
1.0
—
1.0
—
ns
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. Tested per AC Test Load, Figure 2.
4. Measured at
± 200 mV from steady state.
5. This parameter is sampled and not 100% tested.
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