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參數(shù)資料
| 型號(hào)： | MCM69D618 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM |
| 中文描述： | 64K的× 18位同步雙的I / O，雙地址的SRAM |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 175K |
| 代理商： | MCM69D618 |
MCM69F817
7
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(3.6 V
≥ VDD ≥ 3.135 V, 70°C ≥ TA ≥ 0°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VDD
3.135
3.3
3.6
V
I/O Supply Voltage
VDDQ
2.375
3.3
VDD
V
Ambient Temperature
TA
0
—
70
°C
Input Low Voltage
VIL
– 0.3
—
0.8
V
Input High Voltage
VIH
2.0
—
VDD + 0.3
V
Input High Voltage I/O Pins
VIH2
2.0
—
VDDQ + 0.3
V
VIH
20% tKHKH (MIN)
VSS
VSS – 1.0 V
Figure 1. Undershoot Voltage
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input Leakage Current (0 V
≤ Vin ≤ VDD)
Ilkg(I)
—
± 1
A
1
Output Leakage Current (0 V
≤ Vin ≤ VDDQ)
Ilkg(O)
—
± 1
A
AC Supply Current (Device Selected,
MCM69F817–6
All Outputs Open, Freq = Max)
MCM69F817–6.5
Includes VDD and VDDQ
MCM69F817–7
IDDA
—
375
350
325
mA
2, 3, 4
CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at CMOS Levels Vin ≤ VSS + 0.2 V
or
≥ VDD – 0.2 V)
ISB2
—
TBD
mA
5
TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at Vin ≤ VIL or ≥ VIH)
ISB3
—
TBD
mA
5
Clock Running (Device Deselected,
MCM69F817–6
Freq = Max, VDD = Max, All Inputs Toggling at
CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)
ISB4
—
TBD
mA
5
Static Clock Running (Device Deselected,
MCM69F817–6
Freq = Max, VDD = Max, All Inputs Static at Vin ≤ VIL or ≥ VIH)
ISB5
—
TBD
mA
5
Output Low Voltage (IOL = 2 mA) VDDQ = 2.5 V
VOL1
—
0.7
V
Output High Voltage (IOH = – 2 mA) VDDQ = 2.5 V
VOH1
1.7
—
V
Output Low Voltage (IOL = 8 mA) VDDQ = 3.3 V
VOL2
—
0.4
V
Output High Voltage (IOH = – 4 mA) VDDQ = 3.3 V
VOH2
2.4
—
V
NOTES:
1. LBO pin has an internal pullup and will exhibit leakage currents of
± 5 A.
2. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr /tf, pulse level 0 to 3.0 V).
3. All addresses transition simultaneously low (LSB) and then high (MSB).
4. Data states are all zero.
5. Device in Deselected mode as defined by the Truth Table.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, 70
°C ≥ TA ≥ 0°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Min
Typ
Max
Unit
Input Capacitance
Cin
—
4
5
pF
Input/Output Capacitance
CI/O
—
7
8
pF
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