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參數(shù)資料
| 型號： | MCM69D536TQ6R |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM |
| 中文描述： | 32K X 36 DUAL-PORT SRAM, 6 ns, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 175K |
| 代理商： | MCM69D536TQ6R |
MCM69F817
13
MOTOROLA FAST SRAM
K
ADSC
ADDRESS
WRITE
A1
A2
ADSC
(INITIATES
BURST WRITE)
CLOCK STOP
(CONTINUE
BURST WRITE)
WAKE UP ADSC
(INITIATES BURST WRITE)
D(A1)
DATA IN
D(A1+1)
D(A2)
DQx
HIGH–Z
ADV
VIH OR VIL FIXED (SEE NOTE)
NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the
input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control
lines held in an inactive state.
STOP CLOCK WITH WRITE TIMING
相關(guān)PDF資料 |
PDF描述 |
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| MCM69D536TQ8 | 32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM |
| MCM69D536TQ8R | 32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM |
| MCM69D618 | 64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM |
| MCM69D618TQ6 | 64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM |
| MCM69D618TQ6R | 64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM69D536TQ8 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM |
| MCM69D536TQ8R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 36 Bit Synchronous Dual I/O, Dual Address SRAM |
| MCM69D618 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM |
| MCM69D618TQ6 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM |
| MCM69D618TQ6R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM |
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