參數(shù)資料
型號(hào): MCIMX31
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁數(shù): 82/170頁
文件大?。?/td> 1562K
代理商: MCIMX31
i.MX31/i.MX31L Advance Information, Rev. 1.4
82
Freescale Semiconductor
Preliminary
Electrical Characteristics
4.3.8
DPLL Electrical Specifications
The three PLL’s of the MX31/MX31L (MCU, USB, and Serial PLL) are all based on same DPLL design.
The characteristics provided herein apply to all of them, except where noted explicitly. The PLL
characteristics are provided based on measurements done for both sources—external clock source (CKIH),
and FPM (Frequency Pre-Multiplier) source.
4.3.8.1
Electrical Specifications
Table 30
lists the DPLL specification.
CS9
CSPIx_DI Setup Time
t
Smiso
5
ns
CS10
CSPIx_DI Hold Time
t
Hmiso
5
ns
CS11
CSPIx_DRYN Setup Time
t
SDRY
5
ns
Table 30. DPLL Specifications
Parameter
Min
Typ
Max
Unit
Comments
CKIH reference frequency
10
-
100
MHz
CKIL referencer frequency (FPM
enable mode)
32; 32.768,
38.4
MHz
Predivision factor
1
16
PLL reference frequency range
after Predivider
10
35
MHz
Maximum allowed reference clock
phase noise.
10
±
100
μs
Frequency lock time
(FOL mode or non-integer MF)
398
μs
Cycles of divided reference
clock.
Phase lock time
100
μs
In addition to the frequency
PLL Power supply voltage
1.4
1.6
V
Single PLL current consumption
4.4
mA
Maximum allowed PLL supply
voltage ripple
25
mV
F
modulation
< 50 kHz
Maximum allowed PLL supply
voltage ripple
20
mV
F
modulation
< 300 kHz
Maximum allowed PLL supply
voltage ripple
25
mV
F
modulation
< 300 kHz
PLL output clock phase jitter
5.2
ns
Measured on CKO pin
PLL output clock phase jitter
420
ns
Measured on CKO pin
Table 29. CSPI Interface Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Units
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