參數(shù)資料
型號: MCIMX31
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應用處理器
文件頁數(shù): 147/170頁
文件大小: 1562K
代理商: MCIMX31
Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 1.4
Freescale Semiconductor
147
Preliminary
NOTE
All the timings for the SSI are given for a non-inverted serial clock polarity
(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the
polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS shown in the tables and in the figures.
NOTE
All timings are on AUDMUX pads when SSI is being used for data transfer.
NOTE
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
NOTE
For internal Frame Sync operation using external clock, the FS timing is the
same as that of Tx Data, for example, during the AC97 mode of operation.
Table 62. SSI Receiver with Internal Clock Timing Parameters
ID
Parameter
Min
Max
Unit
Internal Clock Operation
SS1
(Tx/Rx) CK clock period
81.4
ns
SS2
(Tx/Rx) CK clock high period
36.0
ns
SS3
(Tx/Rx) CK clock rise time
6
ns
SS4
(Tx/Rx) CK clock low period
36.0
ns
SS5
(Tx/Rx) CK clock fall time
6
ns
SS7
(Rx) CK high to FS (bl) high
15.0
ns
SS9
(Rx) CK high to FS (bl) low
15.0
ns
SS11
(Rx) CK high to FS (wl) high
15.0
ns
SS13
(Rx) CK high to FS (wl) low
15.0
ns
SS20
SRXD setup time before (Rx) CK low
10.0
ns
SS21
SRXD hold time after (Rx) CK low
0
ns
Oversampling Clock Operation
SS47
Oversampling clock period
15.04
ns
SS48
Oversampling clock high period
6
ns
SS49
Oversampling clock rise time
3
ns
SS50
Oversampling clock low period
6
ns
SS51
Oversampling clock fall time
3
ns
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