參數(shù)資料
型號: MCIMX31_07
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processors
中文描述: 多媒體應(yīng)用處理器
文件頁數(shù): 75/108頁
文件大?。?/td> 1235K
代理商: MCIMX31_07
Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 2.3
Freescale Semiconductor
75
4.3.15.5.4
Serial Interfaces,
Electrical Characteristics
Figure 63
depicts timing of the serial interface.
Table 47
lists the timing parameters at display access level.
Figure 63. Asynchronous Serial Interface Timing Diagram
Table 47. Asynchronous Serial Interface Timing Parameters—Access Level
ID
Parameter
Symbol
Min.
Typ.
1
Max.
Units
IP48 Read system cycle time
Tcycr
Tdicpr-1.5
Tdicpr
2
Tdicpw
3
Tdicdr
4
-Tdicur
5
Tdicpr+1.5
ns
IP49 Write system cycle time
Tcycw
Tdicpw-1.5
Tdicpw+1.5
ns
IP50 Read clock low pulse width
Trl
Tdicdr-Tdicur-1.5
Tdicdr-Tdicur+1.5
ns
IP51 Read clock high pulse width
Trh
Tdicpr-Tdicdr+Tdicur-1.5
Tdicpr-Tdicdr+
Tdicur
Tdicdw
6
-Tdicuw
7
Tdicdw-Tdicuw+1.5
Tdicpr-Tdicdr+Tdicur+1.5
ns
IP52 Write clock low pulse width
Twl
Tdicdw-Tdicuw-1.5
ns
IP53 Write clock high pulse width
Twh
Tdicpw-Tdicdw+
Tdicuw-1.5
Tdicpw-Tdicdw+
Tdicuw
Tdicpw-Tdicdw+
Tdicuw+1.5
ns
IP54 Controls setup time for read
Tdcsr
Tdicur-1.5
Tdicur
ns
IP55 Controls hold time for read
Tdchr
Tdicpr-Tdicdr-1.5
Tdicpr-Tdicdr
ns
IP49, IP48
Read Data
IP51, IP53
IP58
IP59
DISPB_SER_RS
DISPB_DATA
(Output)
DISPB_DATA
(Input)
IP56,IP54
IP57, IP55
IP50, IP52
IP61
IP60
IP67,IP65
IP47
IP64, IP66
IP62, IP63
DISPB_SD_D_CLK
read point
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