參數(shù)資料
型號(hào)： MCIMX31_07
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Multimedia Applications Processors
中文描述： 多媒體應(yīng)用處理器
文件頁(yè)數(shù)： 31/108頁(yè)
文件大小： 1235K
代理商： MCIMX31_07
Electrical Characteristics
i.MX31/i.MX31L Advance Information, Rev. 2.3
Freescale Semiconductor
31
4.3.8
DPLL Electrical Specifications
The three PLL’s of the i.MX31/i.MX31L (MCU, USB, and Serial PLL) are all based on same DPLL
design. The characteristics provided herein apply to all of them, except where noted explicitly. The PLL
characteristics are provided based on measurements done for both sources—external clock source (CKIH),
and FPM (Frequency Pre-Multiplier) source.
4.3.8.1
Electrical Specifications
Table 27
lists the DPLL specification.
Table 27. DPLL Specifications
Parameter
Min
Typ
Max
Unit
Comments
CKIH frequency
15
26
1
1
The user or board designer must take into account that the use of a frequency other than 26 MHz would require adjustment to
the DPTC-DVFS table, which is incorporated into operating system code.
2
The PLL reference frequency must be
≤
35 MHz. Therefore, for frequencies between 35 MHz and 70 MHz, program the
predivider to divide by 2 or more. If the CKIH frequency is above 70 MHz, program the predivider to 3 or more. For PD bit
description, see the reference manual.
75
2
MHz
–
CKIL frequency
(Frequency Pre-multiplier (FPM) enable mode)
–
32; 32.768, 38.4
–
kHz FPM lock time
≈
480 μs.
Predivision factor (PD bits)
1
–
16
–
–
PLL reference frequency range after Predivider
15
–
35
MHz 15
≤
CKIH frequency/PD
≤
35 MHz
15
≤
FPM output/PD
≤
35 MHz
PLL output frequency range:
MPLL and SPLL
UPLL
52
190
–
532
240
±
100
MHz
–
Maximum allowed reference clock phase noise.
–
–
ps
–
Frequency lock time
(FOL mode or non-integer MF)
–
–
398
–
Cycles of divided reference clock.
Phase lock time
–
–
100
μs
In addition to the frequency
Maximum allowed PLL supply voltage ripple
–
–
25
mV
F
modulation
< 50 kHz
Maximum allowed PLL supply voltage ripple
–
–
20
mV
50 kHz < F
modulation
< 300 kHz
Maximum allowed PLL supply voltage ripple
–
–
25
mV
F
modulation
> 300 kHz
PLL output clock phase jitter
–
–
5.2
ns
Measured on CLKO pin
PLL output clock period jitter
–
–
420
ps
Measured on CLKO pin
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