參數(shù)資料
型號: MCIMX27
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Multimedia Applications Processor(多媒體應(yīng)用處理器)
中文描述: 多媒體應(yīng)用處理器(多媒體應(yīng)用處理器)
文件頁數(shù): 86/118頁
文件大?。?/td> 1159K
代理商: MCIMX27
i.MX27 Data Sheet, Advance Information, Rev. 0.1
86
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Signal Descriptions
NOTE
All the timings for the SSI are given for a non-inverted serial clock polarity
(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the
polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing is the
same as that of Tx Data, for example, during the AC97 mode of operation.
3.5.17.3
SSI Transmitter Timing with External Clock
Figure 48
and
Figure 49
show the SSI transmitter timing with external clock, and
Table 47
lists the timing
parameters.
Figure 48. SSI Transmitter with External Clock Timing Diagram
SS49
Oversampling clock rise time
3
ns
SS50
Oversampling clock low period
6
ns
SS51
Oversampling clock fall time
3
ns
Table 46. SSI Receiver with Internal Clock Timing Parameters (continued)
ID
Parameter
Min
Max
Unit
SS45
SS33
SS24
SS26
SS25
SS23
AD1_TXC
(Input)
AD1_TXFS (bl)
(Input)
AD1_TXFS (wl)
(Input)
AD1_TXD
(Output)
AD1_RXD
(Input)
Note:
SRXD Input in Synchronous mode only
SS31
SS29
SS27
SS22
SS44
SS39
SS38
SS37
SS46
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