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參數(shù)資料
| 型號： | MCIMX27 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Multimedia Applications Processor(多媒體應用處理器) |
| 中文描述： | 多媒體應用處理器（多媒體應用處理器） |
| 文件頁數(shù)： | 30/118頁 |
| 文件大?。?/td> | 1159K |
| 代理商： | MCIMX27 |
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i.MX27 Data Sheet, Advance Information, Rev. 0.1
30
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Signal Descriptions
CLKMODE[1:0]
These are special factory test signals. To ensure proper operation, do not connect to these
signals.
EXTAL32K
32 kHz crystal input (Note: in the RTC power domain)
XTAL32K
Oscillator output to 32 kHz crystal (Note: in the RTC power domain)
Power_cut
(Note: in the RTC power domain)
Power_on_reset
(Note: in the RTC power domain)
osc32K_bypass
The signal for osc32k input bypass (Note: in the RTC power domain)
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the i.MX27 processor upon
system reset is determined by the settings of these pins. BOOT[1:0] are also used as
handshake signals to PMIC(VSTBY).
JTAG
JTAG_CTRL
JTAG Controller select signal—JTAG_CTRL is sampled during rising edge of TRST. Must be
pulled to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal
test purposes only.
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence JTAG test controller’s state machine. Sampled on rising edge of
TCK.
RTCK
JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is
multiplexed with 1-Wire; thus, utilizing 1-Wire will render RTCK unusable and vice versa; PE16.
Secure Digital Interface (X2)
SD1_CMD
SD Command bidirectional signal—If the system designer does not want to make use of the
internal pull-up, via the Pull-up enable register, a 4. 7K–69 K external pull up resistor must be
added. This signal is multiplexed with CSPI3_MOSI; PE22.
SD1_CLK
SD Output Clock. This signal is multiplexed with CSPI3_SCLK; PE23.
SD1_D[3:0]
SD Data bidirectional signals—If the system designer does not want to make use of the internal
pull-up, via the Pull-up enable register, a 50 K–69 K external pull up resistor must be added.
SD1_D[3] is muxed with CSPI3_SS while SD1_D[0] is muxed with CSPI3_MISO PE21–18.
SD2_CMD
SD Command bidirectional signal. This signal is multiplexed with MSHC_BS; through GPIO
multiplexed with SLCDC1_CS; PB8.
SD2_CLK
SD Output Clock signal. This signal is multiplexed with MSHC_SCLK, through GPIO
multiplexed with SLCDC1_CLK; PB9.
SD2_D[3:0]
SD Data bidirectional signals. SD2_D[3:0] multiplexed with MSHC_DATA[0:3], also through
GPIO SD2_1:0] multiplexed with SLCDC1_RS and SLDCD1_D0; PB7–PB4.
Table 3. i.MX27 Signal Descriptions (continued)
Pad Name
Function/Notes
相關PDF資料 |
PDF描述 |
|---|---|
| MCIMX31_07 | Multimedia Applications Processors |
| MCIMX31 | Multimedia Applications Processors |
| MCL245 | SILICON EPITAXIAL PLANAR DIODE |
| MCL908QT1 | M68HC08 Microcontrollers |
| MCM63R836 | MCM63R836 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MCIMX27_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processor |
| MCIMX27ADSE | 功能描述:開發(fā)板和工具包 - ARM I.MX27 ADS RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| MCIMX27ADSE | 制造商:Freescale Semiconductor 功能描述:Development Kit |
| MCIMX27EC | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processor |
| MCIMX27IPCAM | 功能描述:視頻 IC 開發(fā)工具 I.MX27 IP CAMERA REF RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Boards 類型:YPbPr to RGBHV Converters 工具用于評估:LMH1251 工作電源電壓:5 V |
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