
Signal Descriptions
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
29
NFCLE
NFC Command latch signal, multiplexed with ETMTRACEPKT0; PF1
NFWP_B
NFC Write Permit signal, multiplexed with ETMTRACEPKT1; PF2
NFCE_B
NFC Chip enable signal, multiplexed with ETMTRACEPKT2; PF3
NFRB
NFC read Busy signal, multiplexed with ETMTRACEPKT3; PF0
D[15:0]
Data Bus signal, shared with EMI, PCMCIA, and NFC
PC_CD1_B
PCMCIA card detect signal, multiplexed with ATA ATA_DIOR signal; PF20
PC_CD2_B
PCMCIA card detect signal, multiplexed with ATA ATA_DIOW signal; PF19
PC_WAIT_B
PCMCIA WAIT signal, multiplexed with ATA ATA_CS1 signal; PF18
PC_READY
PCMCIA READY/IRQ signal, multiplexed with ATA ATA_CS0 signal; PF17
PC_PWRON
PCMCIA signal, multiplexed with ATA ATA_DA2 signal; PF16
PC_VS1
PCMCIA voltage sense signal, multiplexed with ATA ATA_DA1 signal; PF14
PC_VS2
PCMCIA voltage sense signal, multiplexed with ATA ATA_DA0 signal; PF13
PC_BVD1
PCMCIA Battery voltage detect signal, multiplexed with ATA ATA_DMARQ signal; PF12
PC_BVD2
PCMCIA Battery voltage detect signal, multiplexed with ATA ATA_DMACK signalPF11
PC_RST
PCMCIA card reset signal, multiplexed with ATA ATA_RESET_B signal; PF10
IOIS16
PCMCIA mode signal, multiplexed with ATA ATA_INTRQ signal; PF9
PC_RW_B
PCMCIA read write signal, multiplexed with ATA ATA_IORDY signal; PF8
PC_POE
PCMCIA output enable signal, multiplexed with ATA ATA_BUFFER_EN signal; PF7
Clocks and Resets
CLKO
Clock Out signal selected from internal clock signals. Refer to the clock controller for internal
clock selection; PF15.
EXT_60M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
EXT_266M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
OSC26M_TEST
This is a special factory test signal. To ensure proper operation, leave this signal as a no
connect.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes active,
all modules (except the reset module, SDRAMC module, and the clock control module) are
reset.
RESET_OUT
Reset_Out—Output from the internal Hreset_b; and the Hreset can be caused by all reset
source: power on reset, system reset (RESET_IN), and watchdog reset.
POR
Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated
by an external RC circuit designed to detect a power-up event.
XTAL26M
Oscillator output to external crystal
EXTAL26M
Crystal input (26 MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when internal
oscillator circuit is shut down.
Table 3. i.MX27 Signal Descriptions (continued)
Pad Name
Function/Notes