參數(shù)資料
型號: MC9S12H128
廠商: Motorola, Inc.
英文描述: Device User Guide
中文描述: 設(shè)備用戶指南
文件頁數(shù): 64/124頁
文件大小: 2125K
代理商: MC9S12H128
MC9S12DP512 Device Guide V01.23
64
2.3.55 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).
2.3.56 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).
2.3.57 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).
2.3.58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).
2.4 Power Supply Pins
MC9S12DP512 power and ground pins are described below.
Table 2-2 MC9S12DP512 Power and Ground Connection Summary
Pin Number
Nominal
Voltage
112-pin QFP
V
DD1, 2
13, 65
2.5 V
Internal power and ground generated by internal regulator
V
SS1, 2
14, 66
0V
V
DDR
41
5.0 V
External power and ground, supply to pin drivers and internal voltage
regulator.
V
SSR
40
0 V
V
DDX
107
5.0 V
External power and ground, supply to pin drivers.
V
SSX
106
0 V
V
DDA
83
5.0 V
Operating voltage and ground for the analog-to-digital converters and
the reference for the internal voltage regulator, allows the supply
voltage to the A/D to be bypassed independently.
86
0 V
V
RL
85
0 V
Reference voltages for the analog-to-digital converter.
V
RH
84
5.0 V
V
DDPLL
43
2.5 V
Provides operating voltage and ground for the Phased-Locked Loop.
This allows the supply voltage to the PLL to be bypassed
independently. Internal power and ground generated by internal
regulator.
VREGEN
97
5V
Internal Voltage Regulator enable/disable
Mnemonic
Description
V
SSA
V
SSPLL
45
0 V
F
For More Information On This Product,
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