參數(shù)資料
型號： MC9S12DJ64VPV
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： MC9S12DJ64 Device User Guide V01.17
中文描述： 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP112
封裝： LQFP-112
文件頁數(shù)： 105/124頁
文件大?。?/td> 2125K
代理商： MC9S12DJ64VPV
105
A.5 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-14
summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block Guide.
Table A-14 Startup Characteristics
A.5.1.1 POR
The release level V
PORR
and the assert level V
PORA
are derived from the V
DD
Supply. They are also valid
ifthedeviceispoweredexternally.AfterreleasingthePORresettheoscillatorandtheclockqualitycheck
are started. If after a time t
CQOUT
no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n
uposc
.
A.5.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
codewhenVDD5isoutofspecificationlimits,theSRAMcontentsintegrityisguaranteedifafterthereset
the PORF bit in the CRG Flags Register has not been set.
A.5.1.3 External Reset
When external reset is asserted for a time greater than PW
RSTL
the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.5.1.4 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
Conditions are shown in
Table A-4
unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
T POR release level
V
PORR
-
-
2.07
V
2
T POR assert level
V
PORA
0.97
-
-
V
3
D Reset input pulse width, minimum input time
PW
RSTL
2
-
-
t
osc
4
D Startup from Reset
n
RST
192
-
196
n
osc
5
D Interrupt pulse width, IRQ edge-sensitive mode
PW
IRQ
20
-
-
ns
6
D Wait recovery startup time
t
WRS
-
-
14
t
cyc
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關PDF資料
PDF描述
MC9S12DJ64VFU MC9S12DJ64 Device User Guide V01.17
MC9S12DJ64MPV MC9S12DJ64 Device User Guide V01.17
MC9S12DJ64MFU MC9S12DJ64 Device User Guide V01.17
MC9S12DJ64CPV MC9S12DJ64 Device User Guide V01.17
MC9S12DJ128CPV MC9S12DT128 Device User Guide V02.09
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