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Appendix A Electrical Characteristics
MC9S08GB/GT Data Sheet, Rev. 2.3
272
Freescale Semiconductor
Output clock ICGOUT frequency
CLKS = 10, REFS = 0
All other cases
f
ICGOUT
f
Extal
(min)
f
lo
(min)
f
Extal
(max)
f
ICGDCLKmax
(max)
MHz
Minimum DCO clock (ICGDCLK) frequency
f
ICGDCLKmin
f
ICGDCLKmax
f
Self
f
Self_reset
8
—
MHz
Maximum DCO clock (ICGDCLK) frequency
Self-clock mode (ICGOUT) frequency
1
—
40
MHz
f
ICGDCLKmin
5.5
f
ICGDCLKmax
10.5
MHz
Self-clock mode reset (ICGOUT) frequency
Loss of reference frequency
2
Low range
High range
Loss of DCO frequency
3
8
MHz
f
LOR
5
50
25
500
kHz
f
LOD
0.5
1.5
MHz
Crystal start-up time
4, 5
Low range
High range
tCSTL
tCSTH
—
—
430
4
—
—
ms
FLL lock time
4, 6
Low range
High range
t
Lockl
t
Lockh
n
Unlock
n
Lock
—
—
2
2
ms
FLL frequency unlock range
–4*N
4*N
counts
FLL frequency lock range
ICGOUT period jitter,
4, 7
measured at f
ICGOUT
Max
Long term jitter (averaged over 2 ms interval)
–2*N
2*N
counts
C
Jitter
—
0.2
% f
ICG
Internal oscillator deviation from trimmed frequency
8
V
DD
= 1.8 – 3.6 V, (constant temperature)
V
DD
= 3.0 V
±
10%, –40
°
C to 85
°
C
1
Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop.
2
Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked
mode if it is not in the desired range.
3
Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external
mode (if an external reference exists) if it is not in the desired range.
4
This parameter is characterized before qualification rather than 100% tested.
5
Proper PC board layout procedures must be followed to achieve specifications.
6
This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external
modes. If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
ICGOUT
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V
DDA
and V
SSA
and variation in crystal oscillator frequency increase the C
Jitter
percentage for a given interval.
8
See
Figure A-10
ACC
int
—
—
±
0.5
±
0.5
±
2
±
2
%
Table A-9. ICG Frequency Specifications (continued)
(V
DDA
= V
DDA
(min) to V
DDA
(max), Temperature Range = –40 to 85
°
C Ambient)
Characteristic
Symbol
Min
Typical
Max
Unit