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Electrical Specifications
MC68HC908GT16 MC68HC908GT8 Data Sheet, Rev. 3
258
Freescale Semiconductor
20.8 5-V Control Timing
Figure 20-1. RST and IRQ Timing
20.9 3-V Control Timing
Figure 20-2. RST and IRQ Timing
Characteristic
(1)
1. V
DD
= 4.5 to 5.5 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
; timing shown with respect to 20% V
DD
and 70% V
SS
, unless otherwise
noted.
2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t
cyc
.
Symbol
Min
Max
Unit
Internal operating frequency
f
OP
(f
Bus
)
t
cyc
t
RL
t
ILIH
—
8
MHz
Internal clock period (1/f
OP
)
122
—
ns
RST input pulse width low
50
—
ns
IRQ interrupt pulse width low (edge-triggered)
50
—
ns
IRQ interrupt pulse period
t
ILIL
Note
(2)
—
t
cyc
Characteristic
(1)
1. V
DD
= 2.7 to 3.3 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
; timing shown with respect to 20% V
DD
and 70% V
DD
, unless otherwise
noted.
2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t
cyc
.
Symbol
Min
Max
Unit
Internal operating frequency
f
OP
(f
Bus
)
t
cyc
t
RL
t
ILIH
—
4
MHz
Internal clock period (1/f
OP
)
244
—
ns
RST input pulse width low
125
—
ns
IRQ interrupt pulse width low (edge-triggered)
125
—
ns
IRQ interrupt pulse period
t
ILIL
Note
(2)
—
t
cyc
RST
IRQ
t
RL
t
ILIH
t
ILIL
RST
IRQ
t
RL
t
ILIH
t
ILIL