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Input/Output (I/O) Ports (PORTS)
MC68HC908GT16 MC68HC908GT8 Data Sheet, Rev. 3
134
Freescale Semiconductor
DDRE4–DDRE0 — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE4–DDRE0, configuring all port
E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 12-19
shows the port E I/O logic.
Figure 12-19. Port E I/O Circuit
When bit DDREx is a 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a 0,
reading address $0008 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Table 12-6
summarizes the operation of the port E pins.
Address:
$000C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-18. Data Direction Register E (DDRE)
Table 12-6. Port E Pin Functions
DDRE
Bit
PTE
Bit
I/O Pin
Mode
Accesses to DDRE
Accesses to PTE
Read/Write
Read
Write
0
X
(1)
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
Input, Hi-Z
(2)
DDRE4–DDRE0
Pin
PTE4–PTE0
(3)
1
X
Output
DDRE4–DDRE0
PTE4–PTE0
PTE4–PTE0
READ DDRE ($000C)
WRITE DDRE ($000C)
RESET
WRITE PTE ($0008)
READ PTE ($0008)
PTEx
DDREx
PTEx
I