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參數(shù)資料
| 型號(hào)： | MC56F8122VFAE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 122/136頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 16BIT 40MHZ 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | 56F8xxx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 40MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 21 |
| 程序存儲(chǔ)器容量： | 32KB（16K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 4K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.25 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 6x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 734 (CN2011-ZH PDF) |
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56F8322 Techncial Data, Rev. 16
86
Freescale Semiconductor
Preliminary
6.5.6.3
IRQ—Bit 10
This bit controls the pull-up resistors on the IRQA pin.
6.5.6.4
Reserved—Bits 9–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.5
JTAG—Bit 3
This bit controls the pull-up resistors on the TRST (This pin is always tied inactive on the 56F8322), TMS
and TDI pins.
6.5.6.6
Reserved—Bits 2–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7
CLKO Select Register (SIM_CLKOSR)
The CLKO select register can be used to multiplex out any one of the clocks generated inside the clock
generation and SIM modules. The default value is SYS_CLK. All other clocks primarily muxed out are
for test purposes only, and are subject to significant unspecified latencies at high frequencies.
The upper four bits of the GPIOB register can function as GPIO, Quad Decoder #0 signals, or as additional
clock output signals. GPIO has priority and is enabled/disabled via the GPIOB_PER. If GPIOB[7:4] are
programmed to operate as peripheral outputs, then the choice between Quad Decoder #0 and additional
clock outputs is made here in the CLKOSR. The default state is for the peripheral function of GPIOB[7:4]
to be programmed as Quad Decoder #0. This can be changed by altering PHASE0 through INDEX as
shown in Figure 6-9.
The CLKOUT pin is not bonded out in this device. Instead, it is offered only as a pad for die-level testing.
Figure 6-9 CLKO Select Register (SIM_CLKOSR)
6.5.7.1
Reserved—Bits 15–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.7.2
PHASEA0 (PHSA)—Bit 9
0 = Peripheral output function of GPIOB[7] is defined to be PHASEA0
1 = Peripheral output function of GPI B[7] is defined to be the oscillator clock (MSTR_OSC, see
6.5.7.3
PHASEB0 (PHSB)—Bit 8
0 = Peripheral output function of GPIOB[6] is defined to be PHASEB0
1 = Peripheral output function of GPIOB[6] is defined to be SYS_CLK2
Base + $A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
PHSA PHSB INDEX HOME
CLK
DIS
CLKOSEL
Write
RESET
0
000
0
1
0
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